Adaptive Parallelism in Non-Volatile Memory Erase Operations
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Solution Overview
Problem
Non-volatile memory devices face challenges with device leakage, leading to increased loads on supply components, reduced signal-to-noise immunity at low voltages, and transconductance degradation, especially with smaller cell sizes, which can result in inefficient erase and program operations and potential failures.
Innovation Solution
The system adaptively reduces device loading by monitoring temperature and adjusting the number of bits programmed or erased in parallel, using subset-programming and subset-erasing operations, to manage device leakage and maintain performance, particularly at higher temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory cells operated in parallel is increased to improve productivity, then program/erase speed increases, but device leakage increases causing charge pump loading and potential operation failure
Solution Approach 1:
The patent dynamically adjusts the degree of parallelism in memory operations based on real-time temperature conditions. At lower temperatures where leakage is manageable, more memory cells are operated in parallel to maximize speed. At higher temperatures where leakage becomes problematic, the system reduces parallelism to maintain reliable charge pump operation, thus adapting the system behavior to current conditions rather than using a fixed parallelism level
Solution Approach 2:
The system changes the operational parameter of parallelism (number of simultaneously operated memory cells) based on temperature measurements. By monitoring temperature and adjusting the parallelism parameter accordingly, the system optimizes the trade-off between speed and reliability, allowing faster operations when conditions permit and more conservative operations when thermal conditions deteriorate
2Reliability
If temperature increases, then device leakage increases causing increased load on charge pumps, but reducing parallelism decreases speed
Solution Approach 1:
The patent implements a feedback mechanism where temperature is continuously monitored and used to adjust the operational parallelism. The temperature sensor provides feedback about thermal conditions, and the control system uses this information to dynamically modify the number of memory cells operated in parallel, creating a closed-loop system that automatically responds to changing thermal conditions to maintain both reliability and performance
Data Source
AI summary
A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.