Memory Refresh Control for Adaptive Error Check and Scrub
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Solution Overview
Problem
Semiconductor memories, particularly volatile types like DRAM, suffer from data loss and unrecoverable errors due to disconnection from power and deterioration over time, necessitating improved error correction and scrubbing mechanisms.
Innovation Solution
A memory device with a refresh control circuit and control logic circuit that performs error check and scrub (ECS) operations based on customizable ECS setting data, adjusting refresh periods and current values to enhance reliability and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check and scrub operations are performed frequently to improve data integrity, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of ECS operation frequency based on detected error rates. The system transitions from static periodic ECS operations to dynamic operations that adapt their frequency according to actual memory health conditions, performing ECS more frequently when errors are detected and less frequently when memory is healthy, thus optimizing the balance between reliability and power consumption
Solution Approach 2:
The system changes the operational parameters of ECS operations based on error occurrence patterns. By monitoring error rates and adjusting the frequency and intensity of ECS operations accordingly, the system optimizes power consumption while maintaining data integrity, performing more aggressive scrubbing only when necessary
2Adaptability or versatility
If multiple ECS modes are supported to meet different client requirements, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the ECS functionality into distinct operational modes (first mode with first ECS period, second mode with second ECS period) that can be independently selected based on client requirements. This modular approach allows the system to offer multiple configurations without requiring a completely different architecture for each mode, managing complexity through structured segmentation of operational parameters
3Reliability
If ECS operations are performed on all memory cell rows, then data integrity is improved, but processing time increases
Solution Approach 1:
The system performs ECS operations selectively rather than uniformly on all memory cell rows. By targeting ECS operations based on error detection results and prioritizing rows that show signs of degradation, the system achieves adequate data integrity protection without the time penalty of exhaustive scrubbing of every memory row
Solution Approach 2:
The patent implements periodic ECS operations with adjustable periods based on memory health. Instead of continuous or uniformly periodic scrubbing of all rows, the system uses error rate information to dynamically adjust the period of ECS operations, performing them more frequently when needed and allowing longer intervals when memory is healthy, thus reducing overall processing time while maintaining reliability
Data Source
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AI summary
A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cell rows; a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller.