Adaptive Memory Write Tracking for SRAM Power Optimization
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Solution Overview
Problem
Conventional memory write operations in SRAM cells often fail due to inadequate discharge or charge rates, leading to increased power consumption when prolonging the write cycle to ensure success, and existing solutions either only track voltage pull-down or cannot adaptively adjust supply voltage for various memory cells with process variations.
Innovation Solution
A memory write tracking device and method using a dummy cell row to simulate physical memory cells, with a variation sensor and judging device to determine an optimal write cycle by adjusting parameters such as bit-line voltage and word-line pulse width, ensuring successful data write operations while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write cycle is prolonged to ensure successful data write operation, then the write reliability is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the write cycle duration adaptive rather than fixed. The write cycle is dynamically adjusted based on the detected write ability of the memory cell, allowing the system to use the minimum necessary time to ensure successful writes while avoiding unnecessary power consumption from prolonged cycles.
Solution Approach 2:
The patent changes the parameter of write cycle duration based on detected write ability characteristics. By varying the write cycle length according to the specific memory cell's properties, the system optimizes the balance between ensuring successful writes and minimizing power consumption.
2Reliability
If the write cycle is prolonged to ensure successful data write operation, then the write ability is improved, but the operation speed decreases
Solution Approach 1:
The patent makes the write cycle duration dynamic and adaptive to the specific memory cell's write ability. This allows the system to achieve high write success rates without uniformly prolonging all write cycles, thereby maintaining overall operation speed and productivity.
Solution Approach 2:
The patent adjusts the write cycle parameter based on detected write ability, enabling the system to optimize each write operation individually. This ensures successful writes while minimizing the impact on overall operation speed.
3Device complexity
If conventional write tracking methods are used that only track voltage pull-down, then the device complexity is reduced, but the measurement precision of write ability is insufficient
Solution Approach 1:
The patent replaces simple voltage tracking with a more sophisticated detection mechanism that measures actual write ability characteristics. This substitution enables more accurate measurement of write ability while maintaining practical device complexity through integrated circuit implementation.
Data Source
AI summary
A memory write tracking device is applied to a data write operation to at least a memory cell row. The memory write tracking device includes a dummy cell row, a variation sensor, a judging device and a word-line pulse generator. The dummy cell row includes a plurality of dummy memory cells for simulating the data write operation to the memory cell row. The variation sensor senses a set of circuit parameters for write ability of the memory cell row. The judging device determines a threshold number according to a change of the set of circuit parameters and sends an enabling signal when a threshold number of the dummy memory cells have been successfully written with the data. The word-line pulse generator determines a write cycle of the data write operation in response to the enabling signal. An associated memory write tracking method is also provided.