Adaptive Mixed-Signal Simulation Partitioning
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Solution Overview
Problem
Traditional mixed-signal design partitioning methods often result in excessive digital-analog crossings and translator cells, hampering simulator performance due to their reliance on signal connectivity processing.
Innovation Solution
A design verification system that classifies mixed-signal circuit designs based on design topology, selectively partitions them into analog and digital components, and inserts translator cells at transitions between block types, allowing for more efficient simulation by using an adaptive partitioning approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional signal connectivity-based partitioning is used, then the partitioning technique is standard and predictable, but the number of translator cells increases excessively hampering simulator performance
Solution Approach 1:
The patent applies dynamics by making the partitioning approach adaptive rather than static. The system dynamically selects between block-level partitioning and signal-connectivity partitioning based on the classification of design topology, allowing the partitioning strategy to adapt to different design characteristics and minimize translator cell insertion while maintaining predictability through systematic decision rules.
Solution Approach 2:
The patent changes the partitioning parameter from fixed signal-connectivity-based methods to classification-based methods that consider design topology characteristics. By classifying designs into different topology types and applying appropriate partitioning strategies for each class, the system optimizes the number of translator cells while preserving standardization through classification rules.
2Productivity
If block-level partitioning is used, then design blocks are preserved and translator cells are reduced, but the classification of design topology must be performed first adding complexity
Solution Approach 1:
The patent applies preliminary action by performing design topology classification before partitioning. This preliminary step identifies the appropriate partitioning strategy to be used subsequently, allowing the system to select the optimal approach (block-level or signal-connectivity-based) based on design characteristics, thereby reducing translator cells while managing complexity through systematic classification.
Solution Approach 2:
The patent segments the partitioning process into distinct phases: classification phase and partitioning phase. By dividing the overall process into these segments, the system can apply different techniques appropriate to each phase, reducing complexity through modularization while achieving the benefit of block-level partitioning when applicable.
3Measurement precision
If translator cells are inserted at every digital-analog crossing, then simulation accuracy is maintained, but the number of translator cells increases excessively
Solution Approach 1:
The patent applies local quality by making translator cell insertion selective rather than universal. Instead of inserting translator cells at every digital-analog crossing, the system identifies and inserts them only at specific boundary locations determined by design topology classification, maintaining simulation accuracy where needed while reducing overall complexity through localized application.
Data Source
AI summary
A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.