Multi-Plane Memory Programming with Adaptive Voltage Steps
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Solution Overview
Problem
In multi-plane memory devices, the programming speed is determined by the slowest plane, leading to inefficiencies and neighbor plane disturb (NPD) due to the use of a uniform programming voltage step size, which affects overall programming efficiency.
Innovation Solution
A method and device that incrementally adjust the programming voltage step size based on verification exceptions, disabling planes with verification issues and using a reduced step size for remaining planes to balance charging and holding times, thereby optimizing programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform programming voltage step size is used for all planes, then the programming process is simple to control, but the programming speed is limited by the slowest plane and neighbor plane disturb occurs
Solution Approach 1:
The patent dynamically adjusts the programming voltage step size parameter based on verification results. Planes that pass verification use a first (larger) step size for faster programming, while planes with verification exceptions use a second (smaller) step size to prevent disturb and ensure proper programming. This parameter adaptation resolves the contradiction by optimizing both speed and reliability.
Solution Approach 2:
The patent applies different programming voltage step sizes to different planes based on their individual verification status. Instead of using a uniform step size for all planes, each plane receives customized programming parameters - fast programming for verified planes and cautious programming for planes with exceptions. This local differentiation eliminates the bottleneck caused by the slowest plane while maintaining control simplicity through automated detection.
2Productivity
If programming voltage step size is increased to improve speed, then programming efficiency increases, but neighbor plane disturb increases
Solution Approach 1:
The patent implements dynamic parameter adjustment by switching between two step sizes based on verification outcomes. The first step size (larger) is used for planes without verification exceptions to maximize speed, while the second step size (smaller) is used for planes with exceptions to prevent neighbor plane disturb. This conditional parameter change resolves the contradiction between efficiency and harmful effects.
Solution Approach 2:
The patent uses verification results as feedback to determine the appropriate programming step size. After each programming attempt, the verification process provides information about whether the plane was successfully programmed. Based on this feedback, the system adjusts the step size for subsequent programming operations, preventing disturb while maintaining efficiency. This feedback mechanism allows the system to adapt to actual plane conditions.
3Object-affected harmful factors
If programming voltage step size is decreased to prevent neighbor plane disturb, then disturb is reduced, but overall programming time increases
Solution Approach 1:
The patent optimizes programming time by selectively applying different step sizes rather than uniformly using the smaller step size. Planes with verification exceptions use the smaller second step size to prevent disturb, while planes without exceptions use the larger first step size to maintain fast programming. This selective parameter application prevents the time loss that would occur if all planes used the conservative step size.
Solution Approach 2:
The patent applies the smaller programming step size locally only to planes that require it (those with verification exceptions), while other planes continue to use the larger step size for fast programming. This localized application of the conservative parameter prevents unnecessary time loss in planes that don't require careful programming, thereby reducing overall programming time while still preventing disturb where needed.
Data Source
AI summary
A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.