Adaptive Multibit Bus Using Voltage Levels to Ease GPU Wire Congestion
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Solution Overview
Problem
Complex GPUs face wire congestion due to the use of single-bit transmission wires, leading to delays and increased power consumption, which limits device usage and efficiency.
Innovation Solution
An adaptive multibit bus is implemented, allowing two bits of data to be transmitted over a single-bit wire by utilizing intermediate voltage levels, enabling higher system frequency without area sacrifice and reducing design value, and dynamically switching between data transmission modes based on voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If single-bit transmission wires are used in complex GPUs, then device area is reduced, but wire congestion increases leading to delays and increased power consumption
Solution Approach 1:
The patent merges multiple data transmission channels into a single wire by utilizing intermediate voltage levels. Specifically, it transmits two bits of data over a single-bit wire by using voltage levels including low, intermediate, and high states, thereby reducing wire count and congestion while maintaining or improving transmission speed
Solution Approach 2:
The patent changes the voltage parameter of the transmission wire to enable multibit communication. By introducing intermediate voltage levels between traditional binary levels, the system encodes multiple bits per wire transmission, resolving the contradiction between area reduction and productivity maintenance
2Area of stationary object
If single-bit transmission wires are used in complex GPUs, then device area is reduced, but power consumption increases
Solution Approach 1:
The patent combines multiple data streams into a single wire transmission using intermediate voltage encoding. This reduces the total number of active wires and their associated switching components, thereby reducing overall power consumption while maintaining area efficiency
Solution Approach 2:
By changing the voltage parameter to include intermediate levels, the system achieves higher data density per wire, reducing the number of wires needed and consequently lowering total power consumption across the GPU interconnect
3Productivity
If intermediate voltage levels are used for multibit transmission, then transmission efficiency increases, but voltage level detection complexity increases
Solution Approach 1:
The patent introduces intermediary detection circuits that simplify the detection of intermediate voltage levels. These mediators convert the multilevel voltage signals into standardized logic levels, reducing the complexity of voltage level detection while maintaining high transmission efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances system performance by increasing frequency at higher voltage levels while reducing power consumption and design complexity, allowing GPUs to enter low power states sooner.
Implementation Method 1
transmitting two bits of data over a single-bit wire by using intermediate voltage levels between a 0 (low) and 1 (high)
Data Source
AI summary
Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.