Adaptive Multibit Bus Using Voltage Encoding for Wire Congestion
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Solution Overview
Problem
Complex GPUs face wire congestion due to the use of single-bit transmission wires, leading to delays and increased power consumption, which limits device usage and efficiency.
Innovation Solution
An adaptive multibit bus is introduced, allowing two bits of data to be transmitted over a single-bit wire by utilizing higher voltage levels, enabling increased system frequency without area sacrifices and reducing design value, and dynamically switching between bit transmission modes based on voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If single-bit transmission wires are used in complex GPUs, then area is reduced, but wire congestion and power consumption increase
Solution Approach 1:
The patent merges multiple bit transmissions into a single wire by utilizing voltage level encoding. Specifically, a single wire transmits multiple bits simultaneously by using different voltage levels to represent different bit combinations, thereby reducing the number of wires needed while maintaining data transmission capacity and reducing power consumption.
Solution Approach 2:
The patent changes the electrical parameter (voltage level) of the transmission wire to encode multiple bits of data. By using different voltage levels (e.g., 0V, V/2, V, 3V/2, 2V) to represent different bit patterns, the system achieves multibit transmission over single-bit wires, resolving the contradiction between area reduction and power consumption.
2Device complexity
If single-bit transmission wires are used in complex GPUs, then device complexity is reduced, but wire congestion and delays increase
Solution Approach 1:
The patent combines multiple data transmission channels into a single wire by using voltage level multiplexing. This merging approach reduces wire congestion and device complexity while maintaining high data transmission efficiency through parallel bit transmission via voltage encoding.
3Speed
If higher voltage levels are used for multibit transmission, then system frequency increases, but power consumption increases
Solution Approach 1:
The patent combines multiple bit transmissions into a single wire using voltage level encoding, which reduces the overall number of signal transitions and wire switches needed. This merging effect compensates for the higher voltage usage by reducing total switching activity, thereby achieving higher system frequency while minimizing power consumption.
4Loss of energy
If adaptive multibit bus is implemented, then power consumption is optimized, but device complexity increases
Solution Approach 1:
The patent implements a dynamic adaptive multibit bus that can switch between different transmission modes (1-bit or 2-bit) based on operating conditions such as voltage level and power requirements. This dynamic adaptability optimizes power consumption by selecting the appropriate transmission mode, while the added control logic complexity is justified by the significant power savings achieved.
Data Source
AI summary
Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.