Adaptive NAND Erase Pulses for Faster Endurance-Safe Block Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The erase process for non-volatile memory devices, such as NAND memory, is a time-consuming operation that strains the memory device and can lead to device failure, necessitating improvements in memory cell endurance and erase times.
Innovation Solution
A sub-block based adaptive erase pulse is employed, where after applying an erase pulse to an erase selected block, one sub-block is verified, and if it fails, the next erase pulse's duration is tuned based on the number of memory cells that fail to verify, ensuring efficient and targeted erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional erase process is used, then the memory device can be erased, but the erase time is long and device strain increases
Solution Approach 1:
The memory block is divided into multiple sub-blocks that can be independently verified. The erase process applies pulses to the entire block but verifies individual sub-blocks, allowing selective continuation or termination based on sub-block status. This segmentation enables faster overall erase times by parallel processing while reducing device strain through early termination when sub-blocks are successfully erased.
Solution Approach 2:
The erase pulse width is dynamically adjusted based on verification results. After each erase pulse, sub-blocks are verified and the duration of subsequent pulses is tuned according to how many sub-blocks fail verification. This dynamic adaptation optimizes the balance between erase speed and device stress, applying stronger pulses only when necessary.
2Productivity
If adaptive pulse tuning is implemented, then erase efficiency improves, but process complexity increases
Solution Approach 1:
The block is segmented into sub-blocks with independent verification capability. This segmentation simplifies the control logic by allowing independent tracking of each sub-block's erase status, making the adaptive pulse tuning more manageable despite the increased overall process complexity.
Data Source
AI summary
To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.