Adaptive NVM Stress Control for Dielectric Reliability
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Solution Overview
Problem
As feature sizes of non-volatile memory (NVM) cells decrease, they become more susceptible to manufacturing variability and require advanced methods to ensure reliability, particularly in enduring repeated program and erase cycles while avoiding dielectric layer damage.
Innovation Solution
A high-voltage stress method that adaptively adjusts stress gate and well bias between erase and program stress modes based on bit cell threshold voltage to prevent over-stressing of dielectric layers, using specific voltage pulses and configurations to manage electric fields within safe limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage stress is applied to NVM cells to improve reliability testing, then the effectiveness of stress testing increases, but the risk of dielectric layer damage increases
Solution Approach 1:
The patent applies dynamics by making the stress gate and well bias adaptive and adjustable between erase stress mode and program stress mode. The bias voltages are dynamically modified based on detected bit cell threshold voltage, allowing the stress conditions to be optimized in real-time to maximize reliability testing effectiveness while preventing dielectric layer damage through automatic adjustment.
Solution Approach 2:
The patent implements feedback by detecting the threshold voltage of bit cells during stress operations and using this information to adaptively adjust the stress gate and well bias. This feedback mechanism ensures that stress conditions remain within safe limits while maintaining high effectiveness for reliability testing, resolving the contradiction between stress intensity and dielectric safety.
2Device complexity
If conventional testing is used to identify manufacturing defects, then the testing process is simple, but it is insufficient for NVMs with smaller geometries susceptible to manufacturing variability
Solution Approach 1:
The patent applies parameter changes by modifying stress gate and well bias voltages based on detected threshold voltage values. This adaptive parameter adjustment enables more sophisticated stress testing that is specifically tailored to the characteristics of small-geometry NVM cells, providing enhanced reliability assessment beyond conventional fixed-parameter testing methods.
3Device complexity
If stress gate and well bias are fixed during stress operations, then the control is simple, but the effectiveness of tunnel oxide stress is reduced
Solution Approach 1:
The patent makes the control dynamic by adaptively adjusting stress gate and well bias between erase and program stress modes based on detected threshold voltage. This dynamic control approach maximizes tunnel oxide stress effectiveness while maintaining manageable complexity through automated adaptation rather than manual intervention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of NVM cells by reducing the risk of dielectric damage and improving the effectiveness of tunnel oxide stress, ensuring consistent performance across multiple cycles.
Implementation Method 1
providing one or more erase stress pulses to the plurality of non-volatile memory cells; providing one or more program stress pulses to the plurality of memory cells
Implementation Method 2
providing one or more erase stress pulses with a predetermined duration such that an electric field of the plurality of non-volatile memory cells is below a dielectric conduction electric field of an insulating layer between a control gate and a charge storage layer
Data Source
AI summary
A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.