Adaptive Oscillation Circuit for Low-Voltage Clock Synchronization

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Solution Overview

Problem

Conventional oscillation circuits face operational issues when the power source voltage decreases, causing functional circuits to delay in following the clock signal, leading to potential operational problems.

Innovation Solution

An oscillation circuit is designed with an electrical current generating portion that decreases oscillation frequency as amplitude decreases, and a control voltage generating portion that adjusts control voltage in response to power source voltage changes, ensuring the oscillation circuit can maintain synchronization with functional circuits even at lower voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the power source voltage is decreased, then power consumption is reduced, but the operational speed of the functional circuit is decreased causing synchronization problems with the clock signal

Engineering Contradiction:
Improvepower consumptionVSAvoidsynchronization between functional circuit and clock signal
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies dynamics by making the oscillation frequency variable rather than fixed. The oscillation circuit automatically adjusts its frequency based on the power source voltage level - operating at lower frequencies when voltage is low and at higher frequencies when voltage is high. This dynamic adaptation ensures that the functional circuit can always operate in synchronization with the clock signal regardless of power consumption requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the frequency parameter of the oscillation circuit based on power source voltage conditions. By detecting the voltage level and adjusting the oscillation frequency accordingly, the system maintains reliable synchronization between the clock signal and functional circuit operations while allowing power consumption to be optimized.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the frequency of the output signal is divided when power source voltage is decreased, then synchronization is maintained, but operational problems occur if the start timing of frequency division is delayed

Engineering Contradiction:
ImprovesynchronizationVSAvoiddelay in frequency division start timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by proactively adjusting the oscillation frequency before synchronization problems can occur. The oscillation circuit monitors power source voltage and preemptively changes frequency to match the functional circuit's operational capabilities, eliminating delays that would otherwise occur with reactive frequency division.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback by continuously monitoring the power source voltage and using this information to adjust the oscillation frequency. This closed-loop control ensures that the clock signal frequency always matches the functional circuit's operational speed, maintaining synchronization without delay.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9525382B2Oscillation circuit
Publication Date: 2016.12.20 LAPIS SEMICON CO LTD
  • US9525382B2 patent drawing
  • US9525382B2 patent drawing
  • US9525382B2 patent drawing

AI summary

An oscillation circuit includes an electrical current generating portion configured to generate an electrical current having an oscillation frequency decreasing as an amplitude thereof is decreased; a control voltage generating portion configured to generate a control voltage having a magnitude decreasing as a magnitude of a power source voltage is decreased; and an electrical current control portion. The electrical current control portion includes a first input terminal connected to the control voltage generating portion for receiving the electrical current; a control terminal connected to the control voltage generating portion for receiving the control voltage; and a first output terminal. The electrical current control portion is configured to reduce the amplitude of the electrical current flowing between the first input terminal and the first output terminal as the magnitude of the control voltage is decreased.