Adaptive PA Bias Circuit for Millimeter-Wave Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In millimeter wave 5G communications, power amplifiers face efficiency challenges due to high frequency and bandwidth, and existing techniques like envelope tracking have performance issues in these applications.
Innovation Solution
An adaptive bias circuit for power amplifiers that adjusts bias levels based on input signal amplitude, using a configuration of transistors and resistors to generate a digitally controllable bias voltage, enhancing output referred 1 dB compression point and saturated output power while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional bias circuits with fixed bias voltages are used, then the circuit structure is simple, but the power amplifier efficiency is poor in millimeter wave 5G applications
Solution Approach 1:
The patent implements dynamic bias voltage adjustment by detecting the envelope of the input signal and using it to control the bias voltage level. The bias circuit transitions from a fixed voltage configuration to a dynamically adjustable one, where the bias voltage varies according to the signal envelope amplitude, thereby improving power amplifier efficiency in millimeter wave 5G applications
Solution Approach 2:
The patent employs feedback mechanisms where the envelope detector monitors the input signal amplitude and feeds this information back to the bias circuit. This feedback loop enables automatic adjustment of the bias voltage to match the signal conditions, optimizing the power amplifier's operating point and efficiency without requiring complex external control systems
2Use of energy by moving object
If envelope tracking techniques are used to improve efficiency, then power amplifier efficiency may be improved, but performance issues arise in 5G millimeter-wave applications due to bandwidth and timing accuracy requirements
Solution Approach 1:
The patent changes the operating parameters of the power amplifier by dynamically adjusting the bias voltage based on the input signal envelope. This parameter adjustment allows the amplifier to operate in different regions (class A, AB, or B) depending on the signal amplitude, improving efficiency while maintaining linearity and performance in millimeter-wave 5G applications without the bandwidth and timing issues of conventional envelope tracking
3Power
If fixed bias voltage is applied to power amplifier, then the circuit is simple to implement, but the output referred 1 dB compression point and saturated output power are limited
Solution Approach 1:
The patent implements dynamic bias voltage adjustment by detecting the envelope of the input signal and using it to control the bias voltage level. The bias circuit transitions from a fixed voltage configuration to a dynamically adjustable one, where the bias voltage varies according to the signal envelope amplitude, thereby improving power amplifier efficiency in millimeter wave 5G applications
Solution Approach 2:
The patent employs feedback mechanisms where the envelope detector monitors the input signal amplitude and feeds this information back to the bias circuit. This feedback loop enables automatic adjustment of the bias voltage to match the signal conditions, optimizing the power amplifier's operating point and efficiency without requiring complex external control systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adaptive bias circuit increases output referred 1 dB compression point and saturated output power, and reduces power consumption by dynamically adjusting bias levels in response to input signal amplitude, improving efficiency in high-frequency, high-bandwidth applications.
Implementation Method 1
a first transistor having its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal... a first resistor connected between the first circuit node and a second circuit node
Implementation Method 2
a second transistor configured to receive a first component of a differential input signal to the PA at its gate terminal... a third transistor configured to receive a second component of a differential input signal to the PA at its gate terminal
Implementation Method 3
The bias circuit is configured to generate a bias voltage for the PA at the second circuit node... dynamically adjusting bias levels in response to input signal amplitude
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A bias circuit (200) for a PA (100) is disclosed. It comprises a first transistor (M1) having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal (GND), a first current source (I1) connected to the first circuit node (x), and a first resistor (R1) connected between the first circuit node (x) and a second circuit node (y). It further comprises a second transistor (M2) configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD), and a third transistor (M3) configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD). The gate terminals of the second transistor (M2) and the third transistor (M3) are configured to be biased by a first voltage (V1). The bias circuit is configured to generate a bias voltage (Vbias) for the PA (100) at the second circuit node (y).