Adaptive Packet Buffering in Network Devices for Lower Latency

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Solution Overview

Problem

Network devices experience unnecessary latency in packet transmission due to the time taken to issue and receive packet data from a packet memory, particularly when the network interface is not congested.

Innovation Solution

A network device employs a memory controller to buffer packet data based on congestion states of network interfaces, using a first buffering scheme for congested interfaces and a second, faster scheme for uncongested interfaces, which includes storing data in an early forward queue without waiting for a read request.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If packet data is stored in packet memory during processing, then packet transmission can be supported, but latency is introduced due to the time taken to issue and receive packet data from memory

Engineering Contradiction:
Improvepacket transmission capabilityVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-storing packet data in the packet memory during the ingress processing stage before the egress processor needs to transmit the packet. This allows the egress processor to immediately access the data without waiting for memory retrieval operations, thereby eliminating the latency that would otherwise be introduced by sequential memory access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the packet processing function into distinct ingress and egress processors that operate independently. The ingress processor handles packet reception and initial processing, while the egress processor handles transmission. This segmentation allows each processor to operate at its own pace and reduces the bottleneck caused by sequential memory access and processing operations.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single buffering scheme is used for all network interfaces, then device complexity is reduced, but latency cannot be optimized for different congestion states

Engineering Contradiction:
Improvebuffering scheme configurationVSAvoidtransmission latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements dynamics by making the buffering scheme adaptive rather than static. The system automatically switches between different buffering approaches based on real-time congestion state detection at each network interface. When congestion is detected, the system dynamically adjusts the buffering strategy to prioritize packet data retrieval, thereby optimizing latency performance without requiring manual configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the congestion state of each network interface is continuously monitored and fed back to the packet processing system. This feedback enables the system to adjust buffering and data retrieval operations in real-time based on actual network conditions, optimizing latency while maintaining manageable device complexity through automated control.

Inventive Principle:
Principle #23Feedback

3Speed

If packet data is retrieved from memory only when needed, then memory access time is reduced, but packet data may not be available when the network interface is ready to transmit

Engineering Contradiction:
Improvememory access speedVSAvoiddata availability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-loading packet data into the packet memory during the ingress processing stage, before the egress processor needs to transmit the packet. This ensures that when the network interface is ready for transmission, the data is already available in the memory, eliminating delays caused by on-demand memory retrieval while maintaining fast access speeds.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by maintaining packet data in the packet memory throughout the processing pipeline. Rather than retrieving data only when needed, the system keeps the data continuously available in memory from ingress processing through egress transmission, ensuring uninterrupted data flow and eliminating idle waiting periods.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250310278A1Packet buffer latency mitigation in a network device
Publication Date: 2025.10.02 MARVELL ASIA PTE LTD
  • US20250310278A1 patent drawing
  • US20250310278A1 patent drawing
  • US20250310278A1 patent drawing

AI summary

A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.