Adaptive Page-Size TLBs for Reducing GPU Translation Misses
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Solution Overview
Problem
TLB misses and page fault exceptions cause significant performance penalties, particularly in graphics processing units (GPUs) when used as accelerators for central processing units (CPUs) with unified memory spaces, impacting efficiency and utilization.
Innovation Solution
Implementing an adaptive page size mechanism in the translation lookaside buffer (TLB) to optimize memory address translation, reducing TLB misses and page fault exceptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed page size is used in the TLB, then the TLB structure is simple and easy to implement, but TLB misses and page fault exceptions increase significantly, causing performance penalties
Solution Approach 1:
The patent implements adaptive page sizes in the TLB, allowing the system to dynamically adjust between different page sizes (e.g., 4KB, 64KB, 1MB) based on the specific memory access patterns and workload requirements. This dynamic adaptation enables the TLB to optimize its behavior for different scenarios without requiring a completely complex restructured design, resolving the contradiction between simplicity and performance.
Solution Approach 2:
The invention changes the page size parameter adaptively based on the virtual address being translated and the current workload characteristics. By modifying this key parameter dynamically rather than using a fixed value, the system achieves higher memory access efficiency while maintaining a relatively straightforward TLB architecture that can handle multiple page sizes.
2Productivity
If adaptive page size is implemented in the TLB, then TLB misses and page fault exceptions are reduced, improving memory access efficiency, but the TLB structure and operation become more complex
Solution Approach 1:
The TLB is segmented into multiple independent sets, each capable of handling different page sizes. This segmentation allows the system to implement adaptive page sizes without requiring a complete redesign of the entire TLB structure. Each set can be independently managed, reducing the overall complexity while still providing adaptive functionality.
Solution Approach 2:
The TLB design incorporates multi-functionality by enabling each TLB set to handle multiple page sizes (4KB, 64KB, 1MB) through configuration bits and adaptable translation logic. This universal capability allows a single TLB structure to serve multiple purposes and adapt to different workload requirements without requiring separate specialized structures for each page size, thereby limiting the increase in complexity.
Data Source
AI summary
Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.