Adaptive Partial Parallel Interconnection for Conductive Line Delay
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices lead to higher yield loss, reduced reliability of electrical interconnections, and increased manufacturing costs due to increased resistance and capacitance in conductive lines, which exacerbate propagation delays and routing area footprints.
Innovation Solution
The proposed adaptive Partial Parallel Interconnection (PPI) scheme shortens conductive lines to minimize resistance-capacitance (RC) delay by determining a merging point that balances resistance and capacitance, reducing the length of added conductive lines and conserving routing area, thereby improving electrical performance and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive lines are extended to connect distant cells in miniaturized semiconductor devices, then electrical interconnection is achieved, but resistance and capacitance increase causing propagation delay
Solution Approach 1:
The conductive line is divided into two segments: a first conductive line and a second conductive line. These segments are arranged in parallel between the first and second cells, creating a segmented interconnection structure that reduces the effective length of each individual conductive path and thereby reduces resistance and capacitance.
Solution Approach 2:
The first and second conductive lines are merged into a parallel interconnection structure. By combining multiple conductive paths between the same two cells, the overall resistance is reduced while the parallel arrangement minimizes the capacitance effect, thus reducing propagation delay.
2Reliability
If conductive lines are extended to connect distant cells, then electrical interconnection is achieved, but routing area footprint increases
Solution Approach 1:
The conductive lines are arranged in parallel, utilizing the spatial dimension more efficiently. Instead of extending a single long conductive line across the routing area, the parallel arrangement distributes the interconnection path across multiple shorter segments, reducing the overall routing area footprint while maintaining electrical connectivity.
3Loss of time
If conductive lines are shortened to reduce RC delay, then propagation delay is reduced, but connection reliability may be compromised
Solution Approach 1:
Multiple conductive lines are merged into a parallel interconnection structure. This combination provides redundant conduction paths, so if one path experiences degradation, the other paths can maintain electrical connectivity, thus preserving reliability while keeping individual line lengths short for reduced RC delay.
Solution Approach 2:
The electrical parameters of the interconnection are optimized by changing the configuration from a single long line to multiple parallel short lines. This parameter change reduces resistance and capacitance values, thereby reducing RC delay while maintaining or improving connection reliability through the parallel structure.
Data Source
AI summary
A method, a non-transitory computer-readable storage medium and a system for a design layout are provided. The method includes: receiving a design layout including a first cell and a second cell; providing a conductive member electrically connected between the first cell and the second cell, the conductive member including a first conductive line and a second conductive line parallel to the first conductive line; determining a first merging point in the first conductive line between the first cell and the second cell; and electrically connecting the first conductive line to the second conductive line at the first merging point.