Adaptive Patterning for Panelized Semiconductor Packaging
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Solution Overview
Problem
In semiconductor device manufacturing, panelized packaging methods like FOWLP face challenges due to misalignment of semiconductor die units during the overmolding process, leading to defective packages and increased yield loss, as conventional mask-based patterning technologies cannot adjust for individual die movement within a panelized format.
Innovation Solution
An adaptive patterning technique using mask-less lithography measures the true position of each semiconductor die unit and forms unit-specific patterns to align with its measured position, allowing for precise alignment and reducing misalignment-related defects through direct write imaging or laser ablation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mask-based patterning is used in panelized packaging, then manufacturing process simplicity is maintained, but misalignment of semiconductor die units during overmolding causes defective packages and increased yield loss
Solution Approach 1:
The patent measures the true position of each semiconductor die unit before the overmolding process and pre-compensates for anticipated misalignment by adjusting the pattern design. This preliminary measurement and compensation action prevents misalignment defects before they occur during manufacturing, thereby improving package quality and reducing yield loss without changing the fundamental mask-based patterning process
Solution Approach 2:
The patent changes the positional parameters of pattern features based on measured die positions. By adjusting the coordinates and locations of pattern elements to account for actual die placement variations, the system maintains alignment accuracy despite die movement during overmolding, thus improving reliability while maintaining productivity
2Manufacturing precision
If adaptive patterning with mask-less lithography is used, then alignment precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies adaptive patterning locally to individual die units that exhibit position variations, rather than changing the entire patterning system. By measuring true positions and adjusting patterns only where needed based on actual die placement, the system improves alignment precision for affected units while maintaining simplicity for units within tolerance, thus balancing precision improvement with process complexity
3Reliability
If larger bond pad openings are used to accommodate misalignment, then manufacturing robustness is improved, but device density and performance are reduced
Solution Approach 1:
The patent measures die positions in advance and pre-adjusts pattern designs to compensate for expected misalignment. This allows the use of smaller, more dense bond pad openings because the compensation already accounts for potential positioning errors, eliminating the need for oversized pads as a safety margin and thereby improving device density while maintaining manufacturing robustness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances package quality and reliability by minimizing yield loss and maintaining compliance with the package outline, enabling smaller bond pad openings and higher density interconnects without requiring changes to the position of UBM pads or BGA balls.
Implementation Method 1
An adaptive patterning technique using mask-less lithography measures the true position of each semiconductor die unit and forms unit-specific patterns to align with its measured position, allowing for precise alignment and reducing misalignment-related defects through direct write imaging or laser ablation.
Data Source
AI summary
An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.