Adaptive PCIe Link Speed Configuration for Power Optimization
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Solution Overview
Problem
Mobile computing devices face challenges in power management due to the increased demand for higher interconnect link speeds, which consume more power and introduce complexity, particularly in devices with constrained power supplies, leading to inefficiencies in battery usage and potential latency issues.
Innovation Solution
Implementing a data rate adaptive PCIe link speed configuration that dynamically adjusts link speeds based on the data rate of the wireless connection, using an algorithm to predict optimal link speeds and adjust accordingly, allowing for power-optimized data delivery and extending battery life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher interconnect link speeds are used to meet increasing processing demands, then data transmission speed and processing capability are improved, but power consumption increases and battery life decreases
Solution Approach 1:
The system dynamically adjusts the PCIe link speed based on real-time data rate requirements from wireless connections. The speed change manager monitors the data rate and transitions the link between different speed states (e.g., Gen 3 to Gen 4) to match the actual throughput needs, avoiding sustained operation at maximum speed when lower rates suffice, thereby reducing power consumption while maintaining performance when needed.
Solution Approach 2:
The invention changes the operational parameters of the PCIe link by adjusting the link speed according to the data rate of wireless connections. When data rates are low, the link operates at lower speeds (e.g., Gen 3), and when data rates increase, the link transitions to higher speeds (e.g., Gen 4), optimizing the balance between performance and power consumption through parameter adaptation.
2Productivity
If higher link speeds are configured to handle peak data rates, then data transmission capability is improved, but device complexity increases
Solution Approach 1:
The system employs dynamic link speed adjustment to manage complexity. Rather than permanently configuring the interconnect for maximum speed (which increases complexity and power consumption), the link adaptively transitions between speed generations based on actual data rate requirements, reducing the effective complexity while maintaining peak capability when needed.
3Use of energy by moving object
If link speed is dynamically adjusted based on data rate, then power efficiency is improved, but latency may increase due to speed transitions
Solution Approach 1:
The system performs preliminary actions by proactively transitioning the PCIe link speed in anticipation of upcoming data bursts. The speed change manager predicts when data rate increases will occur and adjusts the link speed beforehand, reducing the latency impact of speed transitions while maintaining power efficiency during lower activity periods.
Data Source
AI summary
First data is transmitted from a modem of a device to a processor of the device over a point-to-point serial data link at a first one of a plurality of link speeds, where the first data is received at the device over a wireless network connection. The data link transitions to an inactive state following transmission of the first data. Second data is identified that has likewise been received over a wireless network connection, where at least a portion of the second data is received at the device while the data link is in the inactive state. A change from the first speed to a second one of the plurality of link speeds is determined based on historical parameters and predictive parameters. The data link is transitioned to an active state operational at the second link speed to transmit the second data to the processor over the data link.