Adaptive PCIe Link Substate Initiation for Power and Latency Trade-offs
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Solution Overview
Problem
Current PCIe power management schemes introduce significant data communication latencies due to the time required to enter and exit low-power states, which is not optimized for varying link activity and data flow characteristics, limiting battery lifetime and communication performance in mobile devices.
Innovation Solution
Adaptive modification of the entry latency period for the PCIe interface based on link activity and data flow characteristics, where the latency period is increased when excessive transitions to low-power states occur during data bursts and decreased when transitions are minimal, allowing the interface to efficiently manage power consumption while maintaining low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PCIe interface enters low-power states to conserve power, then power consumption is reduced and battery lifetime is extended, but data communication latency increases due to the time required to enter and exit low-power states
Solution Approach 1:
The patent applies dynamics by making the entry latency period adjustable rather than fixed. The controller dynamically modifies the entry latency period based on observed data flow characteristics and link activity patterns, allowing the system to adapt the power state transition timing to match actual communication needs and minimize unnecessary latency while maximizing power savings.
Solution Approach 2:
The patent implements feedback by having the controller monitor and observe data flow characteristics and link activity patterns over time. This observed information is fed back to adjust the entry latency period, creating a closed-loop system that continuously optimizes the balance between power consumption and communication performance based on real-world usage patterns.
2Device complexity
If a fixed entry latency period is used for power state transitions, then the power management scheme is simple to implement, but it cannot adapt to varying link activity and data flow characteristics resulting in suboptimal performance
Solution Approach 1:
The system transitions from a static, fixed entry latency period to a dynamic, adjustable parameter. The controller continuously adapts the entry latency period based on observed data flow characteristics, allowing the power management scheme to respond to varying link activity patterns while maintaining reasonable implementation complexity through automated adaptation.
Solution Approach 2:
The power management scheme performs self-service by automatically adjusting the entry latency period based on observed data flow characteristics without requiring external intervention or complex manual configuration. The controller autonomously monitors link activity and adapts the latency parameter to optimize performance for the specific operational context.
3Loss of time
If the entry latency period is increased to prevent unnecessary power state transitions during data bursts, then communication latency is reduced, but power consumption increases due to longer active periods
Solution Approach 1:
The entry latency period is made dynamic and context-dependent. During data bursts with high link activity, the controller increases the entry latency period to prevent unnecessary transitions and reduce communication latency. During periods of low activity, the latency period is decreased to maximize power savings, thus adapting the timing parameter to match actual operational conditions.
Solution Approach 2:
The system changes the parameter value of the entry latency period based on observed data flow characteristics and link activity patterns. By adjusting this critical timing parameter dynamically, the system optimizes the trade-off between communication performance and power consumption for different operational scenarios without requiring hardware changes.
Data Source
AI summary
Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.