Adaptive Phase Sampling for Low-Power Serial Link Receivers
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Solution Overview
Problem
Conventional serial bit stream communication systems require the receiver to receive and process a separate serializer clock, which consumes significant power and is not optimal in applications where the receiver lacks high-speed clock generating capability.
Innovation Solution
The system employs multiple phase-shifted samplers triggered at specific intervals to recover bits from a serial bit stream without receiving the serializer clock, using a local clock with a frequency lower than the bit rate, and adjusts the sampling phase to align with the serial bit stream signal, allowing for concurrent sampling and bit recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate clock transmission line and clock receiving buffer are used to forward the serializing clock to the receiver, then the receiver can accurately sample the serial bit stream, but the power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the separate clock transmission line and clock receiving buffer from the conventional serial communication system. Instead of transmitting the serializer clock separately, the system uses only the serial bit transmission line, eliminating the harmful clock forwarding path and its associated power consumption while maintaining sampling accuracy through adaptive phase detection
Solution Approach 2:
The receiver generates its own sampling clock locally using a phase detector that adapts to the incoming serial bit stream. This self-generated clock eliminates the need for external clock forwarding, allowing the receiver to service itself without the power-consuming clock transmission infrastructure
2Measurement precision
If the receiver locally generates the serializer clock at high speed, then accurate sampling can be achieved, but the receiver requires high-speed clock generating capability which is not always optimal
Solution Approach 1:
The patent implements a dynamic phase detection and adjustment mechanism where the receiver's local clock is continuously adapted to match the incoming serial bit stream phase. This dynamic adaptation allows accurate sampling without requiring the receiver to have fixed high-speed clock generating capability, making the system more adaptable to different receiver capabilities
Solution Approach 2:
The system changes the frequency parameter of the local sampling clock dynamically, using a phase detector to adjust the clock frequency and phase until optimal sampling is achieved. This parameter adjustment allows the receiver to achieve accurate sampling without requiring predetermined high-speed clock generation capability
3Device complexity
If the serializer clock is embedded in the serial bit stream, then transmission can be simplified, but communication may not be optimal in certain applications
Solution Approach 1:
The patent introduces a phase detector as an intermediary component between the serial bit stream and the sampling clock generation. This intermediary extracts timing information from the data stream itself and uses it to generate the sampling clock, achieving both simplified transmission (no separate clock line) and reliable communication (accurate phase-locked sampling)
Data Source
AI summary
A serial bit stream having a given bit per second rate is received and distributed to a plurality of phase shifted samplers. A multi-phase sampling trigger is generated at a rate lower than the given bit per second rate, and each of the phase shifted samplers is controlled by one of the phases of the multi-phase sampling trigger. The time spacing between phases of the multi-phase sampling trigger is the inverse of the given bit per second rate. The phase of the multi-phase sampling trigger is aligned with the phase of the serial bit, to collectively recover by the plurality of phase shifted samplers a plurality of consecutive bits from the serial bit stream.