Adaptive PLL Loop Bandwidth Control for Lock Speed and Accuracy
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Solution Overview
Problem
Phase-locked loop (PLL) circuits in wireless communication systems face challenges in maintaining optimal performance due to time-variant input signal characteristics, as constant loop bandwidth and damping factor settings fail to adapt to changing environmental conditions, leading to suboptimal locking speed and accuracy.
Innovation Solution
A loop bandwidth adjusting method that dynamically adjusts the operating bandwidth of the PLL unit by measuring and interpolating phase errors between a compensated input signal and a reference clock signal, using a statistics circuit, control circuit, and converting circuit to generate filter coefficients, thereby optimizing the PLL's performance in response to changing input signal conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the loop bandwidth and damping factor of the PLL circuit are kept constant, then the circuit structure remains simple, but the performance cannot persistently maintain the designed optimum value when input signal characteristics change over time
Solution Approach 1:
The patent implements dynamic adjustment of the loop bandwidth by making the bandwidth parameter variable rather than fixed. The bandwidth adjusting unit changes the loop bandwidth based on detected phase error characteristics, allowing the PLL circuit to adapt its performance to time-variant input signals. This resolves the contradiction by introducing controlled dynamics to achieve adaptability while maintaining reasonable system complexity.
Solution Approach 2:
The patent employs feedback mechanisms where phase errors are detected and statistically analyzed, then used to control the bandwidth adjusting unit. The unit receives feedback about phase error variance and adjusts the loop bandwidth accordingly. This feedback loop enables the system to automatically adapt to changing signal conditions without requiring complex external control, balancing adaptability with manageable complexity.
2Speed
If the loop bandwidth is increased to improve locking speed, then the locking speed increases, but the locking accuracy deteriorates
Solution Approach 1:
The patent dynamically adjusts the loop bandwidth based on the statistical characteristics of phase errors. When phase error variance is high, the bandwidth is increased to improve locking speed. When phase error variance is low, the bandwidth is decreased to improve locking accuracy. This dynamic adjustment resolves the speed-accuracy contradiction by adapting the bandwidth to current operating conditions rather than fixing it at a single value.
Solution Approach 2:
The patent changes the loop bandwidth parameter based on detected phase error statistics. The bandwidth adjusting unit modifies the bandwidth parameter in response to varying signal conditions, allowing the system to optimize both locking speed and accuracy at different times. This parameter change strategy enables the PLL to achieve good locking speed during acquisition and good locking accuracy during tracking, resolving the fundamental trade-off.
3Measurement precision
If the loop bandwidth is decreased to improve locking accuracy, then the locking accuracy improves, but the locking speed deteriorates
Solution Approach 1:
The patent makes the loop bandwidth dynamic rather than static, allowing it to be adjusted based on real-time phase error characteristics. During initial locking, the bandwidth is set higher to achieve fast acquisition. Once locked, the bandwidth is reduced to improve tracking accuracy. This temporal dynamic adjustment resolves the contradiction by accepting slower speed only when accuracy is needed, rather than sacrificing speed permanently.
Solution Approach 2:
The patent implements periodic re-evaluation of phase error statistics and corresponding bandwidth adjustments. The system continuously monitors phase error variance and adjusts bandwidth in periodic cycles, allowing it to switch between speed-optimized and accuracy-optimized modes as conditions warrant. This periodic adaptation enables the system to achieve both fast locking and accurate tracking at different phases of operation.
Data Source
AI summary
A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.