Adaptive PLL Driving Voltage for PVT-Stable Clock Generation
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Solution Overview
Problem
PLL circuits face reliability issues when generating high-frequency clock signals due to increased power consumption and degradation of internal elements when applying high voltage to compensate for slow process, voltage, and temperature (PVT) corners.
Innovation Solution
A phase locked loop (PLL) circuit with a frequency calibration circuit that generates a calibration signal by comparing the output frequency with a target frequency, and a regulator that adjusts the driving voltage using resistors and a comparator to minimize power consumption and maintain stability across varying PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high level voltage is applied to compensate for operation in a slow PVT corner, then the clock signal stability is improved, but the power consumption rapidly increases and internal elements are degraded
Solution Approach 1:
The patent implements dynamic voltage adjustment by introducing a regulator circuit that continuously monitors PVT conditions and adapts the driving voltage level accordingly. The regulator includes a comparator that compares the actual operating voltage with a reference voltage, and a control circuit that adjusts the voltage output based on the comparison result, enabling the system to operate at optimal voltage levels rather than continuously applying high voltage
Solution Approach 2:
The patent changes the voltage parameter dynamically based on PVT corner detection. A PVT sensor detects the process-voltage-temperature corner condition, and based on this detection, the regulator adjusts the driving voltage to appropriate levels - applying higher voltage only when necessary for slow corners and reducing voltage for faster corners, thereby resolving the contradiction between stability and power consumption
2Reliability
If a high level voltage is applied to compensate for operation in a slow PVT corner, then the clock signal stability is improved, but internal elements of the load circuit are degraded
Solution Approach 1:
The patent dynamically changes the voltage parameter based on detected PVT conditions. The regulator circuit adjusts the driving voltage level according to the PVT corner, applying high voltage only when necessary for slow corners and reducing voltage for faster corners, thereby preventing unnecessary element degradation while maintaining clock signal stability
Solution Approach 2:
The patent implements a feedback mechanism where the regulator continuously monitors the operating conditions and adjusts the voltage output accordingly. The comparator compares the actual voltage with a reference, and the control circuit uses this feedback to maintain optimal voltage levels, preventing element degradation by avoiding excessive voltage application
Data Source
AI summary
A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.