Adaptive Digital PLL Locking With TDC and Bang-Bang Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing all-digital phase locked loops (ADPLLs) face challenges in combining time-to-digital converter (TDC) and bang-bang (B-B) locking methods, struggling with fine resolution, wide measuring range, and linearity, while B-B based ADPLLs are not suitable for fractional-N PLL architectures.
Innovation Solution
An ADPLL with multiple locking modes that adaptively switches between TDC and B-B based configurations, using a digital phase detector, locking monitor, and loop controller to adjust parameters and switch between locking modes during the frequency locking process, allowing for both coarse and fine frequency tracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TDC based locking method is used, then measurement precision is improved, but device complexity increases due to difficulty in designing TDC with fine resolution, wide measuring range, and good linearity
Solution Approach 1:
The patent implements a dynamic switching mechanism between TDC-based locking mode and B-B based locking mode. The system adaptively selects the appropriate locking method based on operating conditions, allowing the TDC to operate in optimized modes when needed while falling back to simpler B-B methods when TDC complexity becomes prohibitive, thus resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The locking function is segmented into multiple independent locking modes (TDC-based and B-B based). Each mode handles specific operating ranges or conditions independently. This segmentation allows the system to use the high-precision TDC method only when necessary, while using the simpler B-B method for other conditions, reducing overall system complexity while maintaining high measurement precision when needed
2Device complexity
If a B-B based locking method is used, then device complexity is reduced, but adaptability worsens since B-B based ADPLLs are not suitable for fractional-N PLL architectures
Solution Approach 1:
The patent creates a universal locking system that incorporates both TDC-based locking capability (which supports fractional-N PLL architectures) and B-B based locking capability (which offers simplicity). The system can adaptively select which locking method to use based on the architectural requirements, making the overall system universally compatible with different PLL architectures including fractional-N, while maintaining the simplicity advantage of B-B methods when applicable
3Adaptability or versatility
If multiple locking modes are implemented, then adaptability is improved, but device complexity increases due to need for mode switching mechanism
Solution Approach 1:
The system implements a self-service adaptive mode switching mechanism where the locking monitor automatically monitors system state and autonomously selects the appropriate locking mode without requiring external control or complex switching logic. This self-service approach provides multiple locking modes for high adaptability while minimizing the complexity of the mode switching mechanism itself
Data Source
AI summary
An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.