Adaptive PLL Driving Voltage for Stable Clocks Across PVT Corners
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Solution Overview
Problem
High-speed PLL circuits face reliability issues due to increased power consumption and internal element degradation when applying high voltage to compensate for slow process, voltage, and temperature (PVT) corners, leading to unstable clock signal generation.
Innovation Solution
A phase locked loop (PLL) circuit with a frequency calibration circuit that generates a calibration signal by comparing the output frequency with a target frequency, allowing the regulator to adjust the driving voltage, which includes a variable resistor and a comparator to optimize the driving voltage based on the calibration signal, thereby minimizing power consumption and ensuring stable clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high level voltage is applied to compensate for operation in a slow PVT corner, then the clock signal generation stability is improved, but the power consumption rapidly increases and internal elements are degraded
Solution Approach 1:
The patent implements dynamic voltage adjustment by introducing a regulator circuit that automatically modifies the driving voltage level based on real-time detection of PVT corner conditions. The system transitions from static high voltage application to dynamic voltage control, adjusting the voltage level according to actual operating conditions rather than always maintaining maximum voltage.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors its own operating conditions (PVT corner status) and uses this information to adjust the driving voltage through the regulator circuit. This closed-loop control ensures voltage is optimized based on actual performance needs rather than applied at fixed high levels.
2Reliability
If a high level voltage is applied to compensate for operation in a slow PVT corner, then the clock signal generation stability is improved, but internal elements of the load circuit are degraded
Solution Approach 1:
The system dynamically adjusts voltage levels based on detected PVT corner conditions, applying high voltage only when necessary for slow corners and reducing voltage for faster corners. This prevents continuous high-stress operation that causes element degradation while maintaining stability when needed.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on PVT corner detection. The regulator circuit modifies the driving voltage level according to the detected operating conditions, transitioning from fixed high voltage to variable voltage that adapts to process, voltage, and temperature variations.
3Measurement precision
If the driving voltage is increased to maintain frequency in slow PVT corners, then the frequency stability is improved, but the power consumption increases
Solution Approach 1:
The system uses feedback from frequency detection and PVT corner identification to control the regulator circuit. The feedback loop ensures frequency stability is maintained only when necessary by adjusting voltage based on actual corner conditions rather than continuously applying high voltage.
Solution Approach 2:
The driving voltage is made dynamic rather than static, allowing the system to optimize the balance between frequency stability and power consumption by adjusting voltage levels according to real-time PVT corner detection results.
Data Source
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AI summary
A phased locked loop includes: a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.