Adaptive Pole Adjusting Circuit for LDO Stability
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Solution Overview
Problem
Low drop-out (LDO) regulators face challenges in maintaining stability across varying load conditions due to power losses and inefficiencies in adjusting output voltage frequencies, which affects the performance of power management integrated circuits (PMICs).
Innovation Solution
The integration of an adaptive pole adjusting circuit (APAC) within the LDO regulator, which selectively connects an adjusting capacitor to adjust the frequency of the error amplifier's output pole based on load current, enabling adaptive frequency adjustment and improved stability across different load conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed capacitor is used in the error amplifier, then the circuit structure is simple, but the stability cannot be maintained across varying load conditions
Solution Approach 1:
The patent implements dynamic adjustment of the error amplifier's output pole frequency by selectively connecting different capacitors (first capacitor and second capacitor) based on load current magnitude. The adaptive pole adjusting circuit changes the circuit configuration from static to dynamic, allowing the regulator to adapt to varying load conditions and maintain stability across different operating points.
Solution Approach 2:
The patent changes the electrical parameter (capacitance value) of the error amplifier's output pole by selecting between different capacitor values based on load current. This parameter adjustment optimizes the frequency compensation for different load conditions, resolving the stability issue without requiring a completely complex circuit architecture.
2Adaptability or versatility
If a single capacitor value is used, then the device complexity is low, but the adaptability to different load conditions is poor
Solution Approach 1:
The patent introduces dynamic adaptability by implementing an adaptive pole adjusting circuit that automatically selects between different capacitor values based on load current magnitude. This dynamic configuration enables the LDO regulator to adapt to various load conditions (light, medium, heavy loads) without requiring manual intervention or complex external circuitry.
Solution Approach 2:
The patent changes the capacitance parameter of the error amplifier's output pole based on load current conditions. By selecting between a first capacitor value for light loads and a second capacitor value for heavy loads, the system achieves parameter adaptability that optimizes performance across different operating points while maintaining reasonable device complexity.
Data Source
AI summary
An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.