Power-On Reset Circuit with Adaptive Delay for Shorter Standby Time
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Solution Overview
Problem
The existing semiconductor devices with voltage monitoring timers face issues with delayed start of operation and increased power consumption due to varying rise times of supply voltage, leading to wasteful standby times and inefficient power usage.
Innovation Solution
The semiconductor device incorporates a POR circuit, a counter, and a storage section to adjust the timing of the internal reset signal, allowing for customizable count values based on data signals to optimize the reset timing and reduce standby times, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage monitoring timer circuit is used to cancel reset after supply voltage reaches threshold voltage, then the microcomputer can operate after voltage stabilization, but the rise time variation causes delayed start and increased power consumption
Solution Approach 1:
The patent applies dynamics by making the delay time adjustable rather than fixed. The delay time is set based on the actual rise time characteristics of the power supply, allowing the system to adapt to different power supply conditions. This resolves the contradiction by optimizing the standby time to match actual operating conditions, reducing unnecessary delay while ensuring reliable operation.
Solution Approach 2:
The patent changes the parameter of delay time from a fixed value to an adjustable parameter that can be optimized for different power supply rise times. By adjusting this parameter, the system achieves both reliable operation (by ensuring voltage stabilization) and reduced standby time (by minimizing unnecessary delay), thus resolving the technical contradiction.
2Reliability
If a fixed standby time is used in the reset circuit, then the microcomputer operates after voltage stabilization, but the wasteful standby time increases power consumption
Solution Approach 1:
The patent makes the standby time dynamic and adjustable rather than fixed. By adjusting the standby time to match the actual voltage rise characteristics, the system ensures reliable voltage stabilization while minimizing unnecessary standby period, thus reducing power consumption during the reset phase.
Solution Approach 2:
The patent optimizes the standby time parameter based on actual power supply characteristics. By changing this parameter from a conservative fixed value to an optimized value, the system achieves both voltage stabilization assurance and reduced power consumption, resolving the contradiction between reliability and energy efficiency.
3Productivity
If the reset timing is not adjusted, then the circuit operation is simple, but the rise time variation causes delayed start and inefficient power usage
Solution Approach 1:
The patent introduces a dynamic delay time setting mechanism that allows optimization of start-up speed without excessive complexity. The delay time can be adjusted to match different power supply characteristics, enabling fast start-up when possible while maintaining simplicity through a straightforward adjustable parameter rather than a complex control system.
Solution Approach 2:
The patent optimizes the delay time parameter to improve start-up speed. By adjusting this single parameter, the system achieves faster productive operation without introducing complex control mechanisms, thus resolving the contradiction between productivity and device complexity.
Data Source
AI summary
A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.