Power-On Reset Circuit with Adaptive Release Timing
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Solution Overview
Problem
The rise time of supply voltage to rated voltage varies, leading to delayed microcomputer operation and increased power consumption due to inefficient voltage monitoring timer mechanisms in existing semiconductor devices.
Innovation Solution
A semiconductor device with a POR circuit, AND gate, flip flop, counter, and storage section that adjusts the timing of internal reset signal generation and counter operation based on pre-set data signals to optimize power on reset timing, thereby reducing wasteful standby time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage monitoring timer circuit is used to reset the microcomputer after supply voltage reaches threshold voltage, then the microcomputer operation is ensured to start after voltage stabilization, but the standby time is extended and power consumption increases
Solution Approach 1:
The patent applies dynamics by making the reset release timing adjustable rather than fixed. The voltage monitoring timer circuit is configured with adjustable timing parameters that allow the standby period to be optimized based on actual voltage rise characteristics. This enables the system to adapt the reset release timing to match the specific power supply rise time, minimizing unnecessary standby duration while ensuring reliable microcomputer operation.
Solution Approach 2:
The patent implements parameter changes by allowing adjustment of the voltage monitoring timer circuit's timing parameters. Specifically, the standby time period can be modified to correspond to the actual voltage rise time from threshold to rated voltage. This parameter adjustment resolves the contradiction by reducing the fixed standby time to the minimum necessary duration, thereby decreasing power consumption during standby while maintaining operational reliability.
2Reliability
If a fixed standby time is set in the voltage monitoring timer circuit, then the microcomputer operation is ensured to start after voltage stabilization, but the power consumption increases during extended standby periods
Solution Approach 1:
The patent applies dynamics by making the standby time period adjustable rather than fixed. The voltage monitoring timer circuit can be configured with different timing values to match actual operating conditions. This dynamic adjustment capability allows the system to minimize standby duration to the exact time needed for voltage stabilization, reducing energy waste during standby while ensuring reliable microcomputer operation.
Solution Approach 2:
The patent implements parameter changes by allowing modification of the voltage monitoring timer circuit's timing parameters. The standby time can be adjusted to precisely match the voltage rise time characteristics of the power supply. This parameter optimization reduces the standby period to the minimum necessary duration, thereby minimizing power consumption during standby periods while maintaining the reliability of microcomputer operation.
3Reliability
If the reset release timing is delayed to ensure voltage stabilization, then the microcomputer operation reliability is improved, but the start of operation is delayed and power consumption increases
Solution Approach 1:
The patent applies dynamics by making the reset release timing adjustable rather than fixed. The voltage monitoring timer circuit can be configured with optimized timing parameters that balance voltage stabilization requirements with operation start speed. This dynamic adjustment allows the system to release the reset signal as soon as voltage stabilization is achieved, minimizing unnecessary delays and improving operation start speed while maintaining reliability.
Solution Approach 2:
The patent implements parameter changes by allowing adjustment of the voltage monitoring timer circuit's timing parameters to optimize the reset release timing. By configuring the standby time to match the actual voltage rise characteristics, the system can release the reset signal at the optimal moment - neither too early (compromising reliability) nor too late (delaying operation start). This parameter optimization improves productivity by reducing unnecessary delays in operation start while ensuring microcomputer operation stability.
Data Source
AI summary
A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.