Adaptive Power Grid Generation for IC Voltage Drop
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Solution Overview
Problem
The complexity of designing power grids for integrated circuits increases due to rising device counts, placement densities, and switching frequencies, leading to voltage drops that can reduce switching speeds, noise margins, and cause functional failures, as existing designs assume fixed power density and average cell placement.
Innovation Solution
The method involves dividing the chip design into tiles, determining a voltage budget for each tile based on cell activity factors and peak currents, calculating voltage drops, and detecting deviations; the power grid is then adapted by adding or removing power lines to compensate for voltage deficits or surpluses, using a library of power grid sub-structures to address various deviation levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a power grid is designed for average cell placement density and average current consumption, then the preliminary grid design is simplified, but voltage drop violations occur when the chip design is fleshed out in detail
Solution Approach 1:
The patent divides the chip design into multiple tiles, where each tile contains a subset of cells. This segmentation allows the power grid to be analyzed and adapted in localized regions rather than treating the entire chip as a uniform structure. By segmenting the design, the system can identify and correct voltage drop violations in specific tiles without redesigning the entire power grid, thus resolving the contradiction between simplified preliminary design and voltage drop compliance.
Solution Approach 2:
The patent implements a dynamic adaptation process where the power grid design evolves from a preliminary average-based model to a detailed tile-specific model. The system dynamically adjusts the power grid configuration based on actual cell placement densities and current consumption patterns discovered during detailed chip design. This dynamic approach allows the power grid to adapt to real design conditions, ensuring voltage drop compliance while maintaining design efficiency.
2Reliability
If the power grid is designed to compensate for voltage drops, then switching speeds and noise margins are improved, but the design process becomes more complex
Solution Approach 1:
By dividing the chip into tiles and analyzing each tile independently, the patent reduces the complexity of compensating for voltage drops. Instead of redesigning the entire power grid to improve switching speeds and noise margins, the system focuses on localized tile-level adjustments. This segmentation makes the design process more manageable while achieving the desired performance improvements.
Solution Approach 2:
The patent performs preliminary voltage drop analysis and power grid adaptation at the tile level before final chip fabrication. By calculating voltage drops and determining affected vicinities in advance, the system can proactively adjust the power grid configuration to ensure adequate switching speeds and noise margins, rather than discovering and fixing problems after detailed design is complete.
3Measurement precision
If voltage drop analysis is performed at the tile level with affected vicinity calculation, then localized voltage deviations are detected more precisely, but the computational effort increases
Solution Approach 1:
The patent divides the chip into tiles and performs voltage drop analysis on a per-tile basis rather than analyzing the entire chip at once. This segmentation enables precise detection of localized voltage deviations in each tile while reducing the overall computational burden. By focusing analysis on individual tiles and their affected vicinities, the system achieves high measurement precision without the exponential computational cost of full-chip analysis.
Solution Approach 2:
The patent calculates voltage drops and affected vicinities for only the necessary tiles and their neighboring cells, rather than performing exhaustive analysis on all cells in the chip. This partial action approach focuses computational resources on regions where voltage drop violations are most likely to occur, achieving sufficient precision for design validation while significantly reducing computational time compared to complete chip-level analysis.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise management of voltage drops, reducing resistance and improving performance by detecting localized voltage deviations and adapting the power grid accordingly, thereby enhancing switching speeds and reliability.
Implementation Method 1
A power grid distributes power and ground voltages to the devices in a design of an integrated circuit
Implementation Method 2
voltage drops due to the resistance of the power grid interacting with the currents drawn by the various devices on the chip
Data Source
AI summary
A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.