Adaptive Power Multiplexer Layout for Reduced PDN Routing Crowding
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Solution Overview
Problem
Conventional power multiplexing architectures in semiconductor chips inefficiently use routing space, leading to increased routing crowding and semiconductor area usage due to the combination of higher-resistance and lower-resistance switches within a single power multiplexing circuit.
Innovation Solution
Implementing a first type of power multiplexer with higher-resistance switches and a second type with lower-resistance switches, arranged in a daisy chain or loop configuration, where the first type provides enable signals to the second type, allowing for efficient power distribution and reduced routing complexity by separating these switches into distinct multiplexing structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single power multiplexer circuit combines both higher-resistance and lower-resistance switches, then power multiplexing functionality is achieved, but routing space efficiency deteriorates and routing crowding increases
Solution Approach 1:
The patent divides the power multiplexer system into two separate types: first type power multiplexers with higher-resistance switches and second type power multiplexers with lower-resistance switches. This segmentation allows each type to be optimized for its specific switching resistance requirements, improving overall routing space efficiency while maintaining the necessary power multiplexing functionality across different operational modes.
2Adaptability or versatility
If a single power multiplexer circuit combines both higher-resistance and lower-resistance switches, then power multiplexing functionality is achieved, but device complexity increases
Solution Approach 1:
The patent segments the power multiplexer into two distinct types with specialized functions. First type power multiplexers handle higher-resistance switching operations while second type power multiplexers handle lower-resistance switching operations. This segmentation reduces the complexity of individual multiplexer circuits while maintaining the overall adaptability and versatility of the power distribution network.
3Area of stationary object
If higher-resistance switches are used in power multiplexer, then routing space efficiency is improved, but power distribution capability deteriorates
Solution Approach 1:
The patent applies local quality by assigning different switch resistance characteristics to different power multiplexer types based on their specific operational requirements. First type power multiplexers use higher-resistance switches optimized for certain power distribution scenarios, while second type power multiplexers use lower-resistance switches optimized for other scenarios. This local optimization ensures that each multiplexer type achieves the best balance between routing space efficiency and power distribution capability for its specific function.
4Power
If lower-resistance switches are used in power multiplexer, then power distribution capability is improved, but routing space efficiency deteriorates
Solution Approach 1:
The patent implements local quality by configuring second type power multiplexers with lower-resistance switches specifically in locations and contexts where high power distribution capability is the priority. This localized approach ensures that lower-resistance switches are deployed only where their superior power distribution characteristics are most beneficial, while accepting the trade-off of increased routing space usage only in those specific areas.
Data Source
AI summary
A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.