Adaptive Pre-Programming for NAND Flash Multi-Plane Erase

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Solution Overview

Problem

NAND flash memory exhibits a shallow erase phenomenon during partial programming, leading to a widened threshold voltage distribution, which complicates differentiating between stored bit information and increases the fail bit count, especially in multi-plane pre-program operations where secure erase operations may fail to meet uncorrectable error correction criteria.

Innovation Solution

Adaptive and dynamic control of the pre-program pulse duration is implemented based on the number of planes selected for the pre-program operation, with a user-selectable pre-program time increment parameter that can increase non-linearly with the number of planes, ensuring a uniform threshold voltage distribution and enhancing the success rate of secure erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed pre-program pulse duration is used for multi-plane operations, then the operation complexity is reduced, but the threshold voltage distribution becomes non-uniform and secure erase operations fail

Engineering Contradiction:
Improveoperation complexityVSAvoidsecure erase operation success rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic adjustment of the pre-program pulse duration based on the number of planes being operated. The pulse width is extended non-linearly as the number of planes increases, transforming the fixed-duration approach into a variable-duration approach that adapts to multi-plane operation requirements, thereby maintaining uniform threshold voltage distribution across all planes while preserving operational simplicity through automated control.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If the pre-program pulse duration is extended for multi-plane operations, then the threshold voltage distribution uniformity is improved, but the operation time increases

Engineering Contradiction:
Improvethreshold voltage distribution uniformityVSAvoidpre-program operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies periodic pre-program pulses with dynamically adjusted durations to multiple planes in a structured sequence. By distributing the extended pulse duration across the multi-plane operation timeline rather than applying one excessively long pulse, the system achieves uniform threshold voltage distribution while managing the overall operation time more efficiently through time-distributed periodic action.

Inventive Principle:
Principle #19Periodic action

3Manufacturing precision

If a non-linear time increment parameter is used, then the threshold voltage uniformity across planes is maintained, but the control mechanism becomes more complex

Engineering Contradiction:
Improvethreshold voltage uniformityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent incorporates feedback mechanisms where the controller monitors the number of planes being operated and automatically selects the appropriate pre-program pulse width from a set of pre-determined values. This feedback-based adaptive control ensures the correct pulse duration is applied for each multi-plane configuration, maintaining threshold voltage uniformity while simplifying the control interface through automated parameter selection rather than requiring manual calibration.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach consistently maintains a uniform threshold voltage distribution across multiple planes, improving system performance by ensuring successful secure erase operations and preventing shallow erase scenarios, even as the number of planes increases.

Implementation Method 1

Application of VPGM to the control gate generates a high electric field—with a strong negative charge on the transistor's source and drain and a strong positive charge on the control gate—that causes the electrons to migrate from the channel to a charge trapping layer (CTL) of the transistor

Methodology Applied
Scientific EffectElectric field: Electric Field

Implementation Method 2

a flash memory cell may be erased by applying an erase voltage VERA to a source or drain of the transistor to generate an electric field—with a strong positive charge on the cell's source and drain and a strong negative charge on the control gate—which induces a tunneling effect whereby electrons migrate from the CTL to the channel

Methodology Applied
Scientific EffectTunneling effect:

Data Source

PatentUS11955182B2Adaptive pre-programming
Publication Date: 2024.04.09 SANDISK TECHNOLOGIES LLC
  • US11955182B2 patent drawing
  • US11955182B2 patent drawing
  • US11955182B2 patent drawing

AI summary

Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.