Adaptive Precision Multiplier for Mixed Datatype Processing
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Solution Overview
Problem
Existing hardware accelerators for deep neural networks face challenges in efficiently supporting diverse datatypes and precisions, leading to increased training times and resource inefficiencies in multitenant environments.
Innovation Solution
A multiplier is designed to identify and adapt to input value datatypes and precisions, performing operations through sub-multiplication logic, addition, XOR operations, normalization, and rounding, with a multiplexer handling integer and floating-point types, enabling efficient data processing in a MAC array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardware accelerator is designed to support multiple datatypes and precisions, then versatility is improved, but device complexity increases
Solution Approach 1:
The hardware accelerator dynamically reconfigures its operational mode based on the input datatype. The control logic detects whether inputs are integer or floating-point types and activates the appropriate processing path (integer multiplication logic or floating-point logic with exponent/mantissa handling), allowing a single hardware structure to adapt to multiple datatypes without permanent physical changes
Solution Approach 2:
The hardware accelerator is designed with universal components that can handle both integer and floating-point operations. The multiplication logic, addition logic, and data transfer units are configured to perform different functions based on control signals, enabling one hardware structure to serve multiple purposes across different precision requirements (e.g., FP16, BF16, INT8)
2Productivity
If dedicated hardware accelerators are used for DNN operations, then productivity is improved, but adaptability to diverse datatypes decreases
Solution Approach 1:
The hardware accelerator maintains high processing speed by using dynamic configuration rather than static specialization. When floating-point operations are detected, the system activates exponent addition logic and mantissa multiplication logic; when integer operations are detected, it uses simpler integer multiplication logic. This dynamic adaptation allows the system to maintain optimal performance across different precision requirements without requiring separate dedicated hardware for each datatype
Solution Approach 2:
Different parts of the hardware accelerator are optimized for different operations based on local requirements. The exponent handling unit is specifically designed for floating-point operations, while the integer multiplication unit is optimized for integer arithmetic. The control logic selectively activates only the necessary components for the current operation type, maintaining high productivity while supporting diverse precisions
3Measurement precision
If hardware accelerators perform training processes, then accuracy is improved, but training time increases
Solution Approach 1:
The hardware accelerator dynamically adjusts its processing mode based on the specific DNN operation being performed. For operations requiring high precision (such as gradient computation during training), the system activates full floating-point logic with proper exponent and mantissa handling. For operations where lower precision suffices, the system can use optimized integer logic or reduced-precision floating-point logic, thereby maintaining accuracy where needed while reducing training time overall
Data Source
AI summary
An electronic device includes a multiplier including a multiplication logic, a memory including at least one instruction, and at least one processor configured to execute the at least one instruction and to obtain a first input value and a second input value, identify datatypes and precisions of the first input value and the second input value, based on the identified datatypes and precisions, distribute bits of the first input value and bits of the second input value to sub-multiplication logics of the multiplication logic, and obtain at least one output of the multiplication logic based on outputs of the sub-multiplication logics.