Adaptive Prefetch Control for Multi-Slice Processor Memory Bottlenecks

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Solution Overview

Problem

In multi-slice processors, excessive memory controller resource consumption by processing threads can lead to performance bottlenecks, where high demands exceed threshold quantities, impacting quality of service commitments and overall system efficiency.

Innovation Solution

Implementing adaptive prefetch control, where a hypervisor monitors and modifies individual memory controller usage by adjusting prefetch settings for processing threads, dynamically balancing resource allocation to ensure memory controller resources are used efficiently, thereby reducing consumption below threshold levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If processing threads use aggressive prefetch settings to improve memory access speed, then data retrieval performance is improved, but memory controller resource consumption increases above threshold levels

Engineering Contradiction:
Improvememory access speedVSAvoidmemory controller resource consumption
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The system dynamically adjusts prefetch settings based on real-time monitoring of memory controller resource consumption. When consumption exceeds threshold levels, the hypervisor modifies individual thread prefetch settings from aggressive to conservative modes, creating a dynamic adaptation mechanism that responds to system state changes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the prefetch control parameter from static to variable by allowing the hypervisor to modify individual thread prefetch settings. This parameter change enables the system to transition between aggressive and conservative prefetching modes based on resource consumption thresholds

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If individual processing threads control their own prefetch settings autonomously, then thread-level optimization is achieved, but overall memory controller resource management becomes unbalanced

Engineering Contradiction:
Improvethread-level optimization capabilityVSAvoidoverall memory controller resource balance
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The hypervisor acts as an intermediary between processing threads and the memory controller. It monitors aggregate resource consumption and modifies individual thread prefetch settings to maintain overall balance, serving as a mediator that coordinates between individual thread needs and system-wide resource constraints

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If memory controller resource consumption is reduced below threshold levels through prefetch modification, then resource balance is improved, but data retrieval performance may be compromised

Engineering Contradiction:
Improvememory controller resource balanceVSAvoiddata retrieval performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The system applies different prefetch settings to different processing threads based on their individual characteristics and current system state. Rather than uniformly reducing prefetching across all threads, the hypervisor selectively modifies settings for specific threads to maintain resource balance while preserving performance where possible

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11119932B2Operation of a multi-slice processor implementing adaptive prefetch control
Publication Date: 2021.09.14 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11119932B2 patent drawing
  • US11119932B2 patent drawing
  • US11119932B2 patent drawing

AI summary

Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.