Adaptive Program Pulse Selection for Aging Memory Cells
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Solution Overview
Problem
Conventional memory sub-systems face inefficiencies in data writing speed and reliability due to reliance on single criteria for program pulses, leading to erratic behavior and poor write latency, especially as memory cells age and reliability deteriorates.
Innovation Solution
A memory sub-system controller dynamically selects program pulses based on multiple criteria, including program erase cycle counts, read bit error rate, and check failure unit counts, to optimize writing speed and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory sub-systems use single criteria for program pulses, then device complexity is reduced, but reliability deteriorates due to erratic behavior and poor write latency
Solution Approach 1:
The system dynamically adjusts program pulse selection from a static single-criteria approach to a multi-criteria evaluation system that adapts to real-time memory component conditions, including program erase cycle counts and read bit error rates, thereby improving reliability while managing complexity through structured decision-making
Solution Approach 2:
The invention changes the parameters used for program pulse selection from a single criterion to multiple criteria including program erase cycle counts, read bit error rates, and check failure unit counts, allowing the system to optimize write operations based on the actual state of memory components
2Productivity
If memory cells are programmed with higher strength pulses to improve writing speed, then productivity increases, but reliability deteriorates due to increased errors in aged memory cells
Solution Approach 1:
The system dynamically adjusts program pulse strength based on real-time evaluation of memory component conditions, selecting from multiple pulse levels (e.g., first, second, third program pulses) according to program erase cycle counts and error rates, thereby optimizing the balance between writing speed and data accuracy
Solution Approach 2:
The invention changes the program pulse parameter from a fixed high-strength pulse to a variable pulse selection system that adjusts pulse strength based on memory component age and condition, using multiple criteria to determine the appropriate pulse level for each programming operation
3Productivity
If memory sub-systems use fixed program pulses regardless of memory component condition, then device complexity is reduced, but productivity decreases due to poor write latency especially in aged cells
Solution Approach 1:
The system implements dynamic program pulse management that transitions from fixed pulse timing to adaptive pulse selection based on multiple criteria including program erase cycle counts and read bit error rates, improving write latency through real-time optimization while structuring the complexity through systematic evaluation protocols
Solution Approach 2:
The invention performs preliminary evaluation of memory component conditions (program erase cycle counts, read bit error rates, check failure unit counts) before selecting program pulses, allowing the system to pre-determine optimal pulse selection and reduce write latency through proactive adaptation rather than reactive adjustment
Data Source
AI summary
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.