Adaptive Programming Delay in Memory Sub-systems
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Solution Overview
Problem
Conventional two-pass programming methods and sequences are inadequate in fully mitigating program disturb in memory devices as they degrade over time, leading to reduced reliability and increased susceptibility to data errors.
Innovation Solution
An adaptive programming delay scheme is introduced, where the memory sub-system controller determines an adjusted delay between the first and second passes of the programming operation based on the PE cycle count of the memory cells, thereby minimizing program disturb and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional two-pass programming methods are used, then programming operation can be completed, but program disturb occurs in degraded memory devices leading to reduced reliability
Solution Approach 1:
The patent implements dynamic adjustment of the delay period between first and second pass programming operations based on the PE cycle count of memory cells. As memory devices degrade over time (increasing PE cycles), the delay period is increased adaptively to compensate for heightened susceptibility to program disturb, transforming a static programming sequence into a dynamic, condition-responsive process that maintains reliability in degraded devices
Solution Approach 2:
The patent changes the temporal parameter (delay period) of the programming operation based on memory cell wear state. By adjusting the delay duration between programming passes according to PE cycle count, the system modifies the programming parameters to account for device degradation, thereby mitigating program disturb effects in aged memory devices
2Duration of action of stationary object
If memory devices are used over time, then storage capacity is maintained, but susceptibility to program disturb increases due to degradation
Solution Approach 1:
The patent incorporates feedback by monitoring the PE cycle count of memory cells and using this information to adjust subsequent programming operations. The controller continuously tracks device wear state and adapts the programming delay period accordingly, creating a closed-loop system that responds to actual device conditions and maintains reliability throughout the device lifetime
Solution Approach 2:
The patent applies preliminary protective action by inserting a delay period between the first and second pass programming operations. This delay is determined based on the memory cell's wear state and serves as a preventive measure against program disturb before the second pass programming occurs, allowing the memory device to maintain reliability even as it ages
Data Source
AI summary
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a two-pass programming command with respect to a set of memory cells. The processing device is further to determine a value of a metric reflecting a reliability of the set of memory cells. The processing device is further to determine, from a data structure, a delay duration and a subset of the set of memory cells based on the value of the metric. The data structure correlates metric values with respective delay duration values and with respective subsets of memory cells. The processing device is further to perform a two-pass programming operation with respect to the set of memory cells. The two-pass programming operation includes the delay duration between a first pass of the two-pass programming operation and a second pass of the two-pass programming operation.