Adaptive Programming Current Pulses for Phase Change Memory Cells

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Solution Overview

Problem

Existing semiconductor memory apparatuses face challenges in stably programming phase change memory cells with different programming characteristics, as the same programming current pulse may result in varying resistance values due to distinct characteristics among cells.

Innovation Solution

A semiconductor memory apparatus is designed with a first write control code generation unit that updates codes with different cycles, a period control signal generation unit that adjusts timing, and a data write unit that outputs programming current pulses corresponding to these codes, allowing for customized programming current pulses for each memory cell based on its specific characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the same programming current pulse is applied to all memory cells, then the programming process is simple and fast, but the resistance values vary due to different programming characteristics of individual cells

Engineering Contradiction:
Improveprogramming speedVSAvoidprogramming consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the programming current pulse parameters (magnitude and duration) adjustable and adaptive rather than fixed. The system dynamically modifies pulse characteristics based on verification results, transitioning from a static single-pulse approach to a dynamic multi-pulse approach that adapts to individual cell requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes physical parameters (current magnitude and pulse duration) to resolve the contradiction. Different memory cells receive programming pulses with customized parameters - some cells require higher current for shorter duration while others need lower current for longer duration, achieving consistent resistance values across all cells.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If programming current pulse magnitude and duration are adjusted for each memory cell, then programming consistency is improved, but the control complexity increases

Engineering Contradiction:
Improveprogramming consistencyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the programming process into multiple stages: initial programming pulse application, verification step, and conditional re-programming. This segmentation allows the system to handle complexity in a structured way, breaking down the control task into manageable discrete steps rather than requiring continuous complex adjustment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback control by verifying the resistance value after applying the programming pulse and using this verification result to determine whether additional programming pulses are needed. This feedback mechanism enables automatic adjustment without requiring complex external control circuits, as the system self-regulates based on measured outcomes.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If multiple programming pulses with different parameters are applied, then programming precision is improved, but the programming time increases

Engineering Contradiction:
Improveresistance value precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by using verification to determine the minimum necessary programming effort for each cell. Not all cells require multiple pulses - only those that fail verification receive additional programming. This approach avoids unnecessary time expenditure on cells that are already properly programmed while maintaining precision for those that need it.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent uses periodic action through the verify-reprogram cycle. Instead of applying a long continuous programming pulse to all cells, the system uses short programmed pulses separated by verification periods. This periodic approach achieves precise resistance values while minimizing total programming time by interrupting the process to check progress.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables stable programming of phase change memory cells with different characteristics by adjusting the duration and magnitude of programming current pulses, ensuring consistent data storage across multiple cells.

Implementation Method 1

A PCRAM causes a reversible phase change of a phase change material (GST) between a crystalline state and an amorphous state by using Joule heating generated when a current is applied to the phase change material (GST) under certain conditions.

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

the PCRAM stores data by using a phase change of a phase change material according to a temperature condition, that is, a change in a resistance value according to a phase change

Methodology Applied
Scientific EffectPhase change: Phase Change

Data Source

PatentUS8456932B2Semiconductor memory apparatus
Publication Date: 2013.06.04 SK HYNIX INC
  • US8456932B2 patent drawing
  • US8456932B2 patent drawing
  • US8456932B2 patent drawing

AI summary

A semiconductor memory apparatus includes a first write control code generation unit configured to generate a first write control code which is updated with different cycles which have different periods, in response to a programming verification flag signal and a programming enable signal, and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control code which is updated.