Adaptive PUF Post-Processing for Long-Term Key Correctness

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Solution Overview

Problem

Existing PUF post-processing implementations face challenges in balancing hardware cost with yield rate due to fixed error rate thresholds, which can lead to system failure when actual error rates exceed these thresholds, especially under conditions like device aging.

Innovation Solution

Adaptive post-processing of PUFs involves detecting noisy PUF bits, correcting them initially, and storing their locations and values in an Override Bits Table to override them in future key generations, reducing the need for error correction and maintaining long-term correctness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed error rate threshold is used in PUF post-processing, then the system can be designed with fixed hardware cost, but the system fails when actual error rates exceed the threshold due to device aging or other conditions

Engineering Contradiction:
Improvelong-term correctness of PUF-based keysVSAvoidability to accommodate varying error rates
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic error correction by maintaining an override bits table that is updated over time. The system transitions from static fixed-threshold error correction to dynamic adaptation where the override bits table evolves as noisy bits are detected and corrected, allowing the system to adapt to changing error rates while maintaining reliability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs self-correction by automatically detecting noisy PUF bits through error correction, storing their locations in the override bits table, and using these stored locations to preemptively correct errors in future key generations without external intervention

Inventive Principle:
Principle #25Self-service

2Reliability

If the fixed error rate threshold is increased to accommodate higher error rates, then the system maintains operation under worse conditions, but the hardware cost for error correction increases

Engineering Contradiction:
Improveoperation under high error ratesVSAvoidhardware cost for error correction
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary error correction by detecting and correcting noisy PUF bits before they cause key generation failures. The override bits table is proactively populated with locations of noisy bits, enabling preemptive correction that prevents errors from propagating to the final key output

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and isolates the error correction functionality into a separate override bits table mechanism, distinct from the main PUF key generation path. This extraction allows error correction to be performed efficiently on specific noisy bits rather than requiring comprehensive hardware protection for all possible error scenarios

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If fixed Error Correction Logic is designed for a given error rate, then the hardware cost is fixed, but the system fails when actual error rates differ from the design assumptions

Engineering Contradiction:
Improvefixed hardware designVSAvoidcorrectness under varying conditions
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements dynamic error correction by maintaining an override bits table that is updated over time. The system transitions from static fixed-threshold error correction to dynamic adaptation where the override bits table evolves as noisy bits are detected and corrected, allowing the system to adapt to changing error rates while maintaining reliability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms where error correction outcomes are used to update the override bits table. When noisy bits are detected during error correction, their locations are fed back into the override bits table for future correction, creating a continuous improvement loop that enhances reliability

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10129036B2Post-processing mechanism for physically unclonable functions
Publication Date: 2018.11.13 INTEL CORP
  • US10129036B2 patent drawing
  • US10129036B2 patent drawing
  • US10129036B2 patent drawing

AI summary

In accordance with embodiments disclosed herein, there is provided systems and methods for providing a post-processing mechanism for physically unclonable functions. An integrated circuit includes a physically unclonable function (PUF) unit including an adaptive PUF logic. The adaptive PUF logic receives a PUF response having a plurality of bits. The adaptive PUF logic also determines whether a record exists for bit among the plurality of bits in the PUF response. The record includes a stored bit location and a stored bit value corresponding to the stored bit location. The adaptive PUF logic also overrides a bit value of the bit in the PUF response with the stored bit value when it is determined that the record exists for the bit in the PUF response. The bit value of the bit in the PUF response is different from the stored bit value.