Adaptive Pulse Latch Clocking With Dynamic XOR Pulse Width Control
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Solution Overview
Problem
Pulse latches face performance limitations due to varying hold times caused by process, voltage, and temperature (PVT) variations, especially at near threshold voltage (NTV) supply conditions, which are exacerbated by the need for increased inverter counts to account for worst-case hold times, leading to increased hold times and reduced performance.
Innovation Solution
An adaptive pulse generation circuit employing a dynamic XOR-based logic gate and a pull-down keeper circuit generates a pulse signal with a width corresponding to the input-to-output delay of the pulse latch, adapting to PVT variations and minimizing hold time by transitioning based on the states of input and output signals, rather than relying on static worst-case hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of inverters is increased to account for worst-case hold time due to PVT variations, then the reliability is improved, but the hold time increases and performance deteriorates
Solution Approach 1:
The patent implements a dynamic hold time adjustment mechanism that adapts to actual PVT conditions rather than using a static worst-case value. The system monitors process, voltage, and temperature variations and dynamically adjusts the hold time parameter accordingly, allowing the circuit to operate with optimized hold times under normal conditions while maintaining reliability when PVT variations occur.
Solution Approach 2:
The patent changes the hold time parameter from a fixed worst-case value to a variable parameter that adjusts based on actual operating conditions. By implementing continuous or periodic adjustment of the hold time parameter according to monitored PVT conditions, the system achieves both reliability (when adjustments account for variations) and performance (by avoiding excessive hold times during normal operation).
2Use of energy by moving object
If the supply voltage is decreased to reduce power consumption, then the use of energy is improved, but the effect of PVT variations increases causing hold time to vary
Solution Approach 1:
The patent implements a feedback mechanism that monitors supply voltage, process conditions, and temperature to detect PVT variations. The system uses this feedback information to dynamically adjust the hold time parameter, compensating for the increased sensitivity to PVT variations that occurs at lower supply voltages. This allows the system to maintain hold time stability while operating at reduced power consumption levels.
Solution Approach 2:
The patent makes the hold time parameter dynamic and adaptive to operating conditions, particularly at near-threshold voltages where PVT effects are pronounced. By continuously adjusting the hold time based on real-time monitoring of voltage, process, and temperature conditions, the system maintains reliability even when operating at low supply voltages for reduced power consumption.
Data Source
AI summary
Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.