Adaptive Pulse Generator for Stable Pulsed Latch Timing
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Solution Overview
Problem
Pulsed latching apparatuses face challenges in maintaining a stable pulse width under varying operating voltages, leading to potential hold time and setup time violations, which increases error rates due to the sensitivity of pulse width to operating voltage.
Innovation Solution
A pulsed latching apparatus with a pulse signal generator that duplicates the data transmission delay between the input and output terminals to process a clock signal, generating a pulse signal with an adaptive pulse width that adjusts according to the operating voltage, ensuring stable operation across a wide range of voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the pulse width is designed to be wide, then the hold time is increased, but the chance of hold time violation increases
Solution Approach 1:
The pulse width is made dynamically adjustable rather than fixed, allowing it to adapt to different operating conditions. The pulse signal generator includes a delay element whose delay time can be adjusted to change the pulse width according to the operating voltage, resolving the contradiction between needing sufficient pulse width for reliable latching and avoiding excessive pulse width that causes hold time violations.
Solution Approach 2:
The invention changes the parameter of pulse width based on operating voltage conditions. By adjusting the delay time parameter in the pulse signal generator, the system can optimize the pulse width for each operating voltage, preventing both insufficient pulse width (which would cause setup time violations) and excessive pulse width (which would cause hold time violations).
2Duration of action of moving object
If the pulse width is designed to be narrow, then the latching time delay is increased, but the chance of setup time violation and error rate increases
Solution Approach 1:
The pulse width is made dynamically adjustable rather than fixed, allowing it to adapt to different operating conditions. The pulse signal generator includes a delay element whose delay time can be adjusted to change the pulse width according to the operating voltage, resolving the contradiction between needing sufficient pulse width for reliable latching and avoiding excessive pulse width that causes hold time violations.
Solution Approach 2:
The invention changes the parameter of pulse width based on operating voltage conditions. By adjusting the delay time parameter in the pulse signal generator, the system can optimize the pulse width for each operating voltage, preventing both insufficient pulse width (which would cause setup time violations) and excessive pulse width (which would cause hold time violations).
3Device complexity
If the pulse width is optimized for a single operating voltage, then the design is simple, but the stability under wide range of operating voltage cannot be maintained
Solution Approach 1:
The pulse signal generator incorporates a controllable delay element that allows the pulse width to be dynamically adjusted based on operating voltage. This dynamic adjustment capability enables the system to maintain stable operation across a wide voltage range without requiring multiple fixed designs, thus achieving adaptability while keeping the overall device structure relatively simple.
Solution Approach 2:
The invention changes the parameter of pulse width based on operating voltage conditions. By adjusting the delay time parameter in the pulse signal generator, the system can optimize the pulse width for each operating voltage, preventing both insufficient pulse width (which would cause setup time violations) and excessive pulse width (which would cause hold time violations).
Data Source
AI summary
A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.


