Adaptive Variable Length Pulse Synchronizer for Asynchronous Data Capture
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Solution Overview
Problem
Existing digital logic systems struggle to capture and synchronize asynchronous analog data with unknown length and occurrence across varying processes, voltages, temperatures, and clock frequencies, failing to detect pulses faster or slower than the reference clock used in synchronous domains.
Innovation Solution
An adaptive variable length pulse synchronizer is implemented, comprising a state keeper circuit, asynchronous pulse edge detection circuit, pulse edge synchronization circuit, and data synchronization circuit, which detects and synchronizes asynchronous pulses by latching the leading edge of the asynchronous ready signal and transferring data before the data ready indicator is asserted, ensuring predictable data capture regardless of clock rate variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a rigid synchronizer design is used, then the digital logic can capture data at a fixed clock rate, but it cannot guarantee capture of spurious and unpredictable analog data when used for different chips using different clock signals, processes, temperatures and voltages
Solution Approach 1:
The synchronizer uses dynamic pulse width adjustment based on the actual duration of the data ready indicator pulse. The circuit captures the leading edge of the pulse and generates a synchronous pulse whose width adapts to the input pulse duration, allowing reliable data capture across varying clock rates and operating conditions without requiring a fixed rigid timing structure
Solution Approach 2:
The circuit changes the time parameter of the synchronous pulse to match the duration of the asynchronous data ready indicator pulse. By measuring the pulse width of the input signal and adjusting the output pulse width accordingly, the synchronizer adapts to different clock frequencies and timing characteristics across process, voltage, and temperature variations
2Reliability
If the digital logic waits for the data ready indicator, then setup time can be ensured, but the data must be seen earlier than the data ready indicator which creates timing constraints
Solution Approach 1:
The circuit performs preliminary action by capturing the leading edge of the data ready indicator pulse and immediately generating a synchronous pulse that clocks the data into the register before the trailing edge of the data ready indicator occurs. This ensures data is latched into the synchronous domain in advance, providing the required setup time without adding unnecessary delays
3Productivity
If existing synchronization schemes are used, then the system can operate with standard clock rates, but they are unable to ensure detection of an asynchronous pulse that is faster than the reference clock used by the digital logic
Solution Approach 1:
The circuit replaces traditional clock-edge-triggered sampling with a pulse-width-based synchronization mechanism. Instead of relying on the reference clock frequency to detect pulses, the circuit uses the actual width of the data ready indicator pulse to determine when data is valid, enabling detection of asynchronous pulses regardless of whether they are faster or slower than the reference clock
Data Source
AI summary
An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.