Adaptive Queue Sizing for Processor Instruction Fetch
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Solution Overview
Problem
Existing buffer structures in electronic systems are oversized due to worst-case scenario calculations, leading to wasted power and resources, especially in processors supporting multiple instruction sizes, where larger instruction sets result in inefficient use of system resources.
Innovation Solution
Adaptive queue sizing is implemented by using a watermark value to determine when a queue is full, allowing the apparent size of the queue to be adjusted based on instruction set size and runtime conditions, such as branch misprediction rates and pipeline stalls, thereby reducing power consumption and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer size is calculated based on absolute worst case scenario, then system reliability is ensured, but power consumption and resource usage increase
Solution Approach 1:
The patent implements dynamic buffer sizing where the buffer size is adjusted based on runtime conditions such as branch misprediction rates and pipeline stalls. The buffer size is not fixed but adapts to actual system needs, using a watermark value that is modified by runtime events to optimize the balance between reliability and power consumption.
Solution Approach 2:
The patent changes the parameter of buffer size from a static worst-case value to a dynamic value that is adjusted based on runtime conditions. The watermark value, which determines buffer fullness, is modified by events such as branch mispredictions and pipeline stalls, allowing the system to use smaller buffers when conditions permit, thereby reducing power consumption while maintaining reliability.
2Reliability
If buffer size is increased to handle worst case bandwidth discontinuity, then data delivery reliability is improved, but system resource availability deteriorates
Solution Approach 1:
The patent implements dynamic buffer sizing where the buffer size is adjusted based on runtime conditions such as branch misprediction rates and pipeline stalls. The buffer size is not fixed but adapts to actual system needs, using a watermark value that is modified by runtime events to optimize the balance between reliability and power consumption.
Solution Approach 2:
The patent changes the parameter of buffer size from a static worst-case value to a dynamic value that is adjusted based on runtime conditions. The watermark value, which determines buffer fullness, is modified by events such as branch mispredictions and pipeline stalls, allowing the system to use smaller buffers when conditions permit, thereby reducing power consumption while maintaining reliability.
3Productivity
If queue size is fixed for largest instruction set size, then performance for large instructions is maintained, but power efficiency for smaller instruction sets deteriorates
Solution Approach 1:
The patent implements dynamic queue sizing specifically tailored for processors supporting multiple instruction set sizes. The queue size is adjusted based on the current instruction size being executed, using a watermark value that is modified by the instruction size indicator. This allows the system to maintain adequate queue size for large instructions while reducing queue size for smaller instructions, thereby improving power efficiency without sacrificing performance.
Solution Approach 2:
The patent changes the parameter of queue size from a static value based on largest instruction size to a dynamic value that adapts to the current instruction size. The watermark value is modified by events including instruction size indicators, allowing the queue to be appropriately sized for each instruction type, optimizing the balance between performance and power efficiency.
Data Source
AI summary
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.