Adaptive-Biased RDAC Ladder for Low Temperature Reference Drift
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Solution Overview
Problem
Resistive digital-to-analog converters (RDAC) in integrated circuits face linearity performance degradation due to leakage currents, which vary with temperature, process, and supply voltage, leading to unstable output reference voltages and frequency variations in systems like free-running oscillators.
Innovation Solution
A dual resistor ladder DAC circuit with a coarse trim ladder and a fine trim ladder, where the bulk semiconductor substrate regions of NFET switches are driven by a unity gain buffer connected in feedback to receive the output reference voltage, reducing leakage current and temperature variation without increasing circuit area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If RDAC uses MOSFET switches with bulk substrate connected to ground, then the circuit area is reduced, but diode leakages are created causing temperature variation
Solution Approach 1:
The patent introduces an intermediate p-type diffusion region between the bulk substrate and the deep n-well, which acts as a mediator to reduce the diode leakage current. This intermediate structure allows the bulk to be connected to ground while minimizing the harmful leakage effects by creating a more controlled junction path.
Solution Approach 2:
The patent modifies the electrical parameters of the bulk connection by changing the doping concentration and geometry of the p-type diffusion region. By adjusting these parameters, the leakage current is reduced while maintaining the bulk-ground connection, thereby reducing temperature variation without increasing circuit area.
2Object-affected harmful factors
If RDAC uses additional isolated p-well rings to reduce leakage current, then temperature variation is reduced, but circuit area increases
Solution Approach 1:
The patent extracts the essential function of leakage reduction from the complex isolated p-well ring structure and implements it through a simpler p-type diffusion region configuration. This extraction allows achieving the same temperature stability without the area overhead of multiple isolated wells.
Solution Approach 2:
The patent uses a simple p-type diffusion region that can be easily formed during standard CMOS fabrication, replacing the more complex and area-intensive isolated p-well rings. This simpler structure achieves the desired performance with minimal area penalty.
3Area of stationary object
If RDAC uses conventional bulk connection to ground, then circuit area is minimized, but leakage current varies with temperature causing output voltage variation
Solution Approach 1:
The p-type diffusion region serves as an intermediary structure that improves the reliability of the bulk connection by reducing temperature-dependent leakage current, thereby stabilizing the output voltage without increasing circuit area.
Solution Approach 2:
By optimizing the doping concentration and physical dimensions of the p-type diffusion region, the patent changes the electrical parameters to minimize leakage current variation with temperature, thereby improving output voltage stability while maintaining compact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves a fine step temperature variation of 40-44µV over a specified temperature range, significantly improving stability compared to conventional solutions, and can be used in any circuit requiring a stable reference voltage, including free-running oscillators.
Implementation Method 1
a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage
Data Source
Figure 1~2
Figure 3~4B
Figure 5~6B
AI summary
A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.