Adaptive Read Retry with Dynamic Vref Shifts for NAND Decoding
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Solution Overview
Problem
Existing solid state memory devices face challenges in decoding data due to the limitations of fixed reference voltages, which do not adapt to changing conditions such as program/erase count and retention, leading to inefficient read retry processes.
Innovation Solution
The implementation of adaptive read retry optimization using a system with read logic, hard LDPC decoder logic, adaptation logic, and calculation logic that selectively shifts the reference voltage (Vref) by an amount (VDelta) based on a profile of the solid state memory device, allowing for adaptive decoding attempts with varying VDelta values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed reference voltage (Vref) is used for reading memory cells, then the decoding process is simple and fast, but the decoding success rate decreases under varying memory conditions such as program/erase count and retention
Solution Approach 1:
The patent implements dynamic reference voltage adjustment by introducing an adaptation logic that modifies the Vref based on memory conditions. The system uses hard LDPC decoder feedback to detect decoding failures and dynamically shifts Vref by calculated VDelta values, transforming the static Vref into a dynamic parameter that adapts to changing memory states, thereby improving decoding success rate under varying program/erase counts and retention conditions
Solution Approach 2:
The patent changes the voltage parameter Vref adaptively by calculating and applying VDelta shifts based on memory profiles and decoding performance. The calculation logic computes optimal VDelta values, and the adaptation logic applies these shifts to produce Vref_shifted, effectively changing the voltage parameter to match memory conditions and improve decoding reliability
2Reliability
If adaptive reference voltage adjustment is implemented, then the decoding success rate improves, but the read retry process becomes more complex and time-consuming
Solution Approach 1:
The patent performs preliminary actions by pre-calculating VDelta values based on memory profiles before actual read operations. The system characterizes memory devices in advance and stores profile information that guides subsequent adaptive voltage adjustments, reducing the computational burden during time-critical read retry operations and minimizing additional time overhead
Solution Approach 2:
The patent implements a feedback mechanism where the hard LDPC decoder monitors decoding success and provides feedback to the adaptation logic. When decoding fails, the system uses this feedback to trigger adaptive Vref adjustment with pre-calculated VDelta values, creating a closed-loop system that efficiently responds to decoding failures without exhaustive searching, thus reducing read retry time while maintaining high reliability
Data Source
AI summary
Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).