Adaptive Read Retry With Vref Shifting for LDPC Memory Decoding
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Solution Overview
Problem
Existing solid state memory devices face challenges in decoding data due to the inability of hard LDPC decoders to successfully decode data, leading to inefficient read retry processes with fixed reference voltages that do not adapt to changing conditions over time, such as program/erase count and retention.
Innovation Solution
The implementation of adaptive read retry optimization using adaptation logic to selectively shift the reference voltage (Vref) by an amount (VDelta) for soft LDPC decoding, with calculation logic varying VDelta based on the solid state memory device's profile, allowing for iterative decoding attempts with varying voltage references.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed reference voltage (Vref) is used for reading data in solid state memory, then the read operation is simple and fast, but the decoding success rate decreases when memory conditions change over time (program/erase count, retention)
Solution Approach 1:
The reference voltage Vref is transformed from a fixed value to a dynamic value that changes based on memory conditions. The adaptation logic selectively shifts Vref by an amount VDelta to produce Vref_shifted, allowing the read operation to adapt to changing memory characteristics such as program/erase count and retention time, thereby improving decoding success rates without requiring complete redesign of the read process
Solution Approach 2:
The invention changes the voltage parameter Vref dynamically by applying a shift amount VDelta. The calculation logic determines VDelta based on memory profiles, and the adaptation logic applies this shift to create Vref_shifted for soft LDPC decoding. This parameter change enables the system to handle varying memory conditions effectively
2Reliability
If hard LDPC decoding is used with fixed Vref, then the decoding process is fast, but it cannot successfully decode data when memory conditions deteriorate
Solution Approach 1:
The system performs preliminary hard LDPC decoding with the original Vref before attempting soft LDPC decoding with shifted voltage. This preliminary action allows the system to quickly handle easy cases while reserving more time-consuming soft decoding with adaptive voltage adjustment for difficult cases, optimizing the overall time efficiency
Solution Approach 2:
The system uses feedback from the hard LDPC decoding result to determine whether to proceed to soft LDPC decoding. When hard decoding fails, the system triggers soft decoding with adaptively shifted voltage, creating a feedback loop that improves decoding success while managing time consumption effectively
3Reliability
If adaptive voltage shifting is implemented, then decoding success rate improves, but the system complexity and calculation overhead increase
Solution Approach 1:
The decoding system is segmented into two distinct paths: hard LDPC decoding using original Vref and soft LDPC decoding using shifted Vref_shifted. This segmentation allows each decoder to be optimized for its specific purpose, with the adaptation logic serving as a bridge that selectively routes between them based on decoding success
Solution Approach 2:
The adaptation logic acts as an intermediary between the fixed Vref system and the variable Vref_shifted system. It calculates the shift amount VDelta based on memory profiles and applies it selectively, mediating between the simplicity of fixed voltage and the adaptability of variable voltage without requiring complete system redesign
Data Source
AI summary
Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).