Adaptive Read-Threshold Selection for NAND Flash Reliability

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Solution Overview

Problem

Enterprise SSDs face challenges in managing bit-error rates (BER) and uncorrectable error-correction code (UECC) failure rates due to varying conditions in NAND flash memory blocks, which affect quality of service (QoS) and require an adaptive read-threshold scheme to optimize performance.

Innovation Solution

A memory system with a performance tracker and read-threshold selector that monitors read attempts at an initial threshold, estimates performance of alternative thresholds, and determines an optimal read-threshold for use based on quality metrics, employing multi-armed bandit algorithms to balance exploration and exploitation for optimal read-threshold selection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed read-threshold scheme is used, then device complexity is reduced, but bit-error rate and UECC failure rate increase due to varying NAND block conditions

Engineering Contradiction:
Improveread-threshold scheme complexityVSAvoidbit-error rate and UECC failure rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a dynamic read-threshold selection mechanism that adapts thresholds based on real-time NAND block conditions. The system monitors block characteristics such as program-erase cycle count, retention time, and page-read frequency, then dynamically selects optimal read-thresholds from multiple available thresholds to maintain low BER and UECC rates while managing complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the read-threshold parameter based on detected NAND block conditions. Multiple read-threshold levels are maintained, and the appropriate threshold is selected by analyzing block-specific parameters such as the number of program-erase cycles experienced, retention time duration, and page-read frequency, thereby optimizing reliability without excessive complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If adaptive read-threshold selection is implemented, then bit-error rate decreases, but device complexity increases due to performance tracking and threshold selection mechanisms

Engineering Contradiction:
Improvebit-error rateVSAvoidperformance tracker and threshold selector complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements self-service through automated performance tracking and threshold selection. The performance tracker autonomously monitors read operations and block conditions, automatically updating threshold selections without external intervention. This reduces the operational burden and effective complexity while maintaining low BER through continuous adaptation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent employs feedback mechanisms where read performance outcomes are monitored and fed back to adjust future threshold selections. The system tracks successful and failed reads under different threshold conditions, using this feedback to refine threshold selection decisions and minimize BER over time, thereby managing complexity through learned patterns.

Inventive Principle:
Principle #23Feedback

3Reliability

If multiple read-thresholds are evaluated, then UECC failure rate reduces, but read latency increases due to additional evaluation steps

Engineering Contradiction:
ImproveUECC failure rateVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary evaluation of multiple read-thresholds during idle periods or low-priority operations to pre-determine optimal thresholds for different block conditions. By preparing threshold selections in advance based on block characteristics, the system reduces UECC failure rates while minimizing latency during actual read operations, as the threshold selection is already determined.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different read-thresholds to specific local regions or blocks of NAND memory based on their individual conditions rather than using a global threshold. Each block or region is evaluated and assigned its own optimal threshold, reducing UECC failures locally while avoiding the need to evaluate all possible thresholds for every read operation, thereby controlling overall latency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10847231B2Memory system with adaptive read-threshold scheme and method of operating such memory system
Publication Date: 2020.11.24 SK HYNIX INC
  • US10847231B2 patent drawing
  • US10847231B2 patent drawing
  • US10847231B2 patent drawing

AI summary

Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.