Adaptive Read Training for 3D Memory Devices
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Solution Overview
Problem
Three dimensional memory crosspoint devices face inefficiencies in read operations due to varying transmission line propagation times and the need for frequent profile switching, leading to lower read efficiency as the number of devices increases, as they require extensive memory and cache space for individual training profiles.
Innovation Solution
Implementing adaptive read training techniques where each 3DXP device stores and adjusts its own timing settings, using a delay locked loop circuit to self-adjust read output timing, reducing the reliance on the memory controller for timing settings and allowing for a shared read profile across devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual training profiles are stored for each 3DXP device in the memory controller, then read accuracy is improved, but memory and cache space requirements increase significantly
Solution Approach 1:
The patent divides the training profile storage function from the memory controller to the individual 3DXP devices themselves. Each device maintains its own timing settings and read profiles locally, segmenting the previously centralized storage function. This eliminates the need for large memory and cache space in the controller while preserving read accuracy through device-specific profile storage.
Solution Approach 2:
Each 3DXP device performs self-service by storing and managing its own training profiles and timing settings internally. The devices autonomously adjust their read output timing without requiring the memory controller to manage extensive profile storage, thereby reducing the controller's memory and cache requirements while maintaining measurement precision.
2Measurement precision
If frequent profile switching is performed to accommodate varying transmission line propagation times, then read accuracy is improved, but read efficiency decreases
Solution Approach 1:
The patent implements dynamic timing adjustment where each 3DXP device autonomously modifies its read output timing based on its specific transmission line propagation characteristics. This dynamic adaptation eliminates the need for frequent profile switching between devices, as each device operates with optimized timing settings tailored to its physical characteristics, thereby improving both read accuracy and efficiency.
Solution Approach 2:
The system changes the timing parameters (such as read output timing and data strobe timing) directly at the device level rather than switching between predefined profiles. This parameter adjustment approach allows continuous optimization of read accuracy for varying propagation times without the overhead of profile switching, thus maintaining high read efficiency.
3Device complexity
If centralized timing management is used in the memory controller, then coordination between devices is simplified, but device complexity increases
Solution Approach 1:
The patent segments the timing management function from the centralized memory controller to individual 3DXP devices. Each device incorporates its own timing adjustment capabilities, including delay-locked loop circuits and trim registers, thereby distributing the complexity rather than concentrating it in the controller. This segmentation reduces controller complexity while enhancing overall system adaptability.
Solution Approach 2:
Each 3DXP device performs self-configuration and self-adjustment of timing parameters without requiring complex centralized management. The devices autonomously program their internal delay elements and trim settings based on their specific electrical characteristics, eliminating the need for sophisticated controller-based timing coordination while maximizing adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves read accuracy and efficiency by allowing each 3DXP device to adaptively adjust its read output timing, eliminating the need for frequent profile switching and reducing memory requirements, resulting in improved data transmission and processing efficiency across multiple devices.
Implementation Method 1
a delay locked loop circuit to self-adjust read output timing
Data Source
AI summary
A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein the memory controller is configured to derive a read profile for each of the one or more memory devices to account for a time propagation delay of data being sent via the data bus during read operations of the one or more memory devices.