Memory System Read-Voltage Correction for Inter-Cell Interference
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in accurately reading data due to inter-cell interference effects that cause threshold voltage distributions to shift over time, leading to increased error rates and potential data read failures.
Innovation Solution
A memory system with a controller that utilizes a shift table and history table to adjust read voltages based on inter-cell interference, employing refresh read operations and block copy operations to maintain accurate data reading, and includes a flag table to manage these processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed repeatedly on memory cells, then data retrieval is maintained, but inter-cell interference causes threshold voltage distribution to shift and read errors increase
Solution Approach 1:
The patent applies preliminary action by performing refresh read operations periodically before inter-cell interference severely degrades data accuracy. The controller monitors read error rates and initiates refresh operations to restore threshold voltage distributions before errors accumulate to unacceptable levels, preventing rather than curing the harmful interference effect.
Solution Approach 2:
The patent implements feedback through the controller monitoring read error rates and using this information to determine when refresh read operations are necessary. The controller adjusts operation timing based on actual error conditions, creating a closed-loop system that responds to inter-cell interference effects in real-time.
2Reliability
If refresh read operations are performed to correct threshold voltage shifts, then data accuracy is maintained, but operation time increases
Solution Approach 1:
The patent applies partial action by performing refresh read operations only on specific blocks or pages rather than the entire memory array. The controller selectively targets areas with the highest error rates or most critical data, reducing the total time required for maintenance operations while still achieving adequate error correction.
3Reliability
If block copy operations are performed to restore data, then read errors are corrected, but manufacturing complexity increases
Solution Approach 1:
The patent uses copying by creating a backup copy of the logical block mapping table in the host memory device. This copy serves as a fallback reference when threshold voltage shifts cause read errors, allowing the system to restore correct mappings without requiring complex real-time recalibration mechanisms.
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.