Adaptive Read Voltage for Non-Volatile Memory Drift
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Solution Overview
Problem
Non-volatile memory (NVM) technologies face challenges in designing efficient mechanisms for repeated accesses to memory cells due to voltage drift after writing data, leading to potential read failures, especially in 'hot' memory addresses that are frequently accessed, where traditional lockout times can be counterproductive and reduce system performance.
Innovation Solution
Implementing a system that allows immediate reading of memory addresses after a write operation by using a drift read voltage that accounts for voltage drift during the drift period and switching to a standard read voltage once the cells have stabilized, along with a temporal access history buffer to track write timestamps for prioritized memory addresses to calculate the appropriate read voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lockout time is implemented to prevent read failures during voltage drift, then read reliability is improved, but system performance and access speed deteriorate due to delays in accessing hot memory addresses
Solution Approach 1:
The patent applies dynamics by making the read voltage adaptive rather than static. The read voltage dynamically adjusts based on the time elapsed since the last write operation, allowing the system to optimize between read reliability and performance. During the drift period, the read voltage is adjusted to compensate for voltage drift, while after stabilization, the standard read voltage is used, eliminating the need for lockout times.
Solution Approach 2:
The patent changes the read voltage parameter based on temporal conditions. By monitoring the time since the last write operation and adjusting the read voltage accordingly, the system compensates for voltage drift during the drift period and uses standard voltage after stabilization, resolving the contradiction between reliability and performance.
2Productivity
If immediate reading is allowed after write operations, then system performance and access speed are improved, but read failures occur due to voltage drift in frequently accessed memory addresses
Solution Approach 1:
The patent applies preliminary action by tracking the time of last write operation in advance. This temporal information is used to determine whether a read operation should use an adjusted voltage or standard voltage, allowing immediate reading without lockout times while preventing read failures through proactive voltage adjustment.
Solution Approach 2:
The patent implements feedback by continuously monitoring the time elapsed since the last write operation and using this information to adjust the read voltage. This closed-loop approach ensures that reads during the drift period use appropriate voltage compensation, while reads after stabilization use standard voltage, maintaining both performance and reliability.
3Device complexity
If a standard read voltage is used for all read operations, then device complexity is reduced, but read accuracy deteriorates during the voltage drift period
Solution Approach 1:
The patent transitions from a static read voltage approach to a dynamic one. The read voltage becomes time-dependent, adjusting automatically based on whether the read operation occurs during or after the voltage drift period. This dynamic adjustment maintains read accuracy without significantly increasing device complexity, as the voltage adjustment logic can be implemented in existing control circuitry.
Data Source
AI summary
Technology for a system operable to write and read data from memory is described. The system can include memory and a memory controller. The memory controller can send an instruction to write data to a NVM address in the memory at a time of last write (TOLW). The memory controller can determine to read the data from the NVM address in the memory at read time. The memory controller can determine a read voltage to read the data from the NVM address in the memory at the read time. The read voltage can be determined based on a difference between the TOLW and the read time, and a modeled voltage drift for the NVM address over a period of time.