Adaptive Receiver Pre-Cursor Cancellation for High-Speed ISI

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Solution Overview

Problem

Current high-speed interface designs face challenges in effectively canceling inter-symbol interference (ISI), particularly pre-cursor ISI, which affects the performance of communication channels between transmitter and receiver circuits, and complicates adaptation within the receiver circuit.

Innovation Solution

The proposed solution involves a data receiver circuit configuration that includes a summer circuit to combine input signals with feedback signals, a clock generator circuit to generate a clock signal, and precursor and post-cursor compensation circuits to mitigate ISI effects. This configuration samples data symbols using voltage offsets and adjusts operational parameters to adapt to channel changes, enabling effective cancellation of both pre-cursor and post-cursor ISI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If pre-cursor ISI cancellation is implemented in the receiver circuit, then data recovery performance is improved, but circuit complexity and difficulty of adaptation increase

Engineering Contradiction:
Improvedata recovery performanceVSAvoidreceiver circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The receiver circuit is segmented into distinct functional blocks: summer circuit for combining signals, clock generator for timing, data slicer for sampling, precursor compensation circuit for pre-cursor ISI cancellation, and post cursor compensation circuit for post-cursor ISI cancellation. This segmentation allows each block to perform a specific function, improving data recovery while managing complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The precursor compensation circuit performs preliminary action by canceling pre-cursor ISI before the data symbol is sampled and processed. By using feedback from previously recovered data symbols to generate compensation signals that are added to the incoming signal in advance, the circuit prepares the signal for optimal sampling, thereby improving measurement precision without requiring complex real-time processing during the critical sampling window.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If multiple voltage offsets are used for sampling data symbols, then adaptability to channel changes is improved, but device complexity increases

Engineering Contradiction:
Improveadaptation to channel changesVSAvoidsampling circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The data slicer circuit employs multiple voltage offsets that can be dynamically adjusted based on channel conditions. The circuit adapts to channel changes by selecting or adjusting the appropriate voltage offsets for sampling, allowing it to maintain optimal performance across varying transmission conditions. This dynamic adaptability improves versatility while the automated adjustment mechanisms help manage the complexity of having multiple offset levels.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The receiver circuit uses feedback from previously recovered data symbols to adjust the voltage offsets and compensation parameters. The post cursor compensation circuit generates feedback signals based on previously recovered symbols, which are then used to adjust the sampling voltage offsets and precursor compensation levels. This feedback mechanism enables automatic adaptation to channel changes without requiring manual intervention, improving versatility while managing complexity through automated control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11240073B2Adapative receiver with pre-cursor cancelation
Publication Date: 2022.02.01 ORACLE INT CORP
  • US11240073B2 patent drawing
  • US11240073B2 patent drawing
  • US11240073B2 patent drawing

AI summary

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.