Adaptive Receiver Clock Recovery With Stable Phase Locking
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Solution Overview
Problem
Existing adaptive receiver systems face instability in phase clock adjustment near the lock point, leading to reduced jitter tolerance and potential false locks due to interference between phase clock adjustment and equalizer control, and lack effective methods for high-speed processing and inter-symbol interference reduction.
Innovation Solution
An adaptive receiver system with an equalizer circuit, phase comparison circuits, a clock adjustment circuit, a pattern detection circuit, and an adaptive control filter circuit, which generate phase comparison signals to stabilize the phase of the sampling clock, reduce interference, and adjust equalization strength based on detected patterns to maintain high-frequency noise tolerance and ensure stable adaptive operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase comparison signal output continues near lock point, then phase adjustment and equalizer control can be performed continuously, but stability of phase adjustment and equalizer operation deteriorates
Solution Approach 1:
The patent implements periodic action by using two distinct phase comparison operations that alternate in a periodic manner: a first phase comparison for coarse phase adjustment and a second phase comparison for fine phase adjustment near the lock point. This periodic alternation prevents continuous unstable feedback while maintaining control functionality.
Solution Approach 2:
The patent segments the phase comparison function into two distinct operations: a first phase comparison circuit for initial phase alignment and a second phase comparison circuit for precision phase matching near the lock point. This segmentation divides the continuous control problem into discrete stages, improving stability at each stage.
2Speed
If phase adjustment and equalizer control are performed simultaneously based on same sampling values, then system responds quickly to changes, but false lock occurs due to interference between controls
Solution Approach 1:
The patent segments the control functions by using different sampling values for phase adjustment and equalizer control. The first phase comparison uses one set of sampling values while the equalizer control uses another set, preventing interference between the two control loops while maintaining responsive operation.
Solution Approach 2:
The patent introduces an intermediary mechanism by using a sampling value conversion unit that transforms sampling values between different control functions. This intermediary conversion process ensures that phase adjustment and equalizer control operate on properly transformed data, preventing false lock while maintaining coordination.
3Device complexity
If no equalizer is provided in clock data recovery circuit, then circuit complexity is reduced, but inter-symbol interference cannot be reduced
Solution Approach 1:
The patent merges the clock data recovery function with the equalizer function into an integrated adaptive receiver system. The equalizer is combined with the clock recovery circuitry, allowing simultaneous performance of both functions while managing complexity through integrated design rather than separate independent circuits.
Data Source
AI summary
A phase comparison circuit outputs a first phase comparison signal indicating whether or not an edge of an equalization signal is in a first interval between sampling timing and timing having a first predetermined phase advance, and outputs a second phase comparison signal indicating whether or not the edge of the equalization signal is in a second interval between the sampling timing and timing having a second predetermined phase delay. A determination circuit compares a predetermined comparison target pattern with output patterns of the first and second phase comparison signals corresponding to each bit of a detection data pattern.