Adaptive DRAM Refresh Scheduling via Flow and Blockage Score Tracking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional DRAM refresh scheduling techniques result in increased latency and bandwidth loss due to fixed intervals and sequences, which can lead to collisions with memory access patterns, particularly affecting high-priority read accesses and inefficiently managing quarantine windows.

Innovation Solution

An adaptive refresh scheduling method that employs pre-check and hindsight-based sequence selection to minimize traffic collisions by tracking flow and blockage scores across multiple refresh sequences, favoring sequences with high flow and low blockage, and dynamically updating scores to optimize refresh timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If fixed interval and sequence refresh scheduling is used, then refresh operations are simple to implement, but latency increases and bandwidth is lost due to collisions with memory access patterns

Engineering Contradiction:
Improveease of implementationVSAvoidlatency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements dynamic refresh scheduling where the memory controller adapts refresh sequences based on observed memory access patterns. Instead of fixed intervals, the system monitors traffic patterns and adjusts refresh timing to avoid collisions with high-priority accesses, thereby reducing latency while maintaining DRAM integrity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by monitoring memory access patterns and using this information to adjust refresh scheduling decisions. The controller observes traffic patterns and modifies refresh sequences accordingly, creating a closed-loop system that optimizes performance based on actual usage conditions.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If fixed sequence refresh is used, then implementation is straightforward, but bandwidth is lost due to quarantine windows blocking memory accesses

Engineering Contradiction:
Improveease of implementationVSAvoidbandwidth
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent dynamically adjusts refresh sequencing based on observed memory access patterns. By monitoring which ranks are accessed and when, the system reorders refresh operations to occur during periods of lower activity, minimizing the impact of quarantine windows on overall bandwidth while still maintaining DRAM integrity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary monitoring of memory access patterns before making refresh scheduling decisions. By observing traffic patterns in advance, the controller can predict periods of lower activity and schedule refresh operations during these windows, thereby minimizing bandwidth loss while maintaining straightforward implementation through pattern-based rules.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If adaptive refresh scheduling with flow and blockage score tracking is used, then bandwidth and latency are improved, but device complexity increases

Engineering Contradiction:
ImprovebandwidthVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller performs self-optimization by automatically monitoring its own traffic patterns and adjusting refresh schedules without external intervention. The system uses simple counters for flow and blockage scores that are automatically updated based on observed accesses, enabling the controller to self-adjust to optimal performance without complex configuration or external control.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the parameters of refresh scheduling based on observed conditions. By adjusting refresh timing and sequence parameters in response to measured traffic patterns, the system achieves adaptive optimization. The complexity is managed by changing only the timing parameters while maintaining the same basic refresh mechanism, rather than redesigning the entire refresh system.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9922693B2Adaptive refresh scheduling for memory
Publication Date: 2018.03.20 ALTERA CORP
  • US9922693B2 patent drawing
  • US9922693B2 patent drawing
  • US9922693B2 patent drawing

AI summary

The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.