Adaptive Sampling Phase Selection for Serial Signal Jitter

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Solution Overview

Problem

Existing serial communication systems, such as DigRF interfaces, face challenges in maintaining low bit error rates due to phase noise and jitter, especially when the receiver clock is not synchronized with the transmitter clock, leading to errors in data recovery and requiring redundant error correction at higher protocol levels.

Innovation Solution

The implementation of an adaptive phase sequence system that dynamically adjusts sampling phases during signal regeneration, using oversampling and differential error comparisons to determine the optimal sampling phase, thereby reducing bit errors and phase noise impacts, and allowing for continuous data sampling across all phases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If oversampling is used to achieve low bit error rate, then data recovery accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvedata recovery accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system uses the synchronization sequence itself as the reference for determining optimal sampling phases. The known synchronization pattern enables the receiver to automatically identify which sampling phases yield correct data values, eliminating the need for external calibration or complex training sequences. This self-service approach achieves accurate sampling phase selection while keeping the system relatively simple.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically selects sampling phases based on the detected quality of the data signal. When signal quality deteriorates (e.g., due to phase noise or jitter), the system can switch to alternative sampling phases that are more robust to the current impairments. This parameter change strategy allows adaptive optimization of sampling timing without requiring a fixed, overly complex sampling architecture.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If a fixed reference sampling phase is selected from synchronization sequence, then initial data recovery is enabled, but the system cannot adapt to signal degradation during frame transmission

Engineering Contradiction:
Improveinitial data recoveryVSAvoidadaptability to signal degradation
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The system continuously monitors the quality of the data signal during frame transmission by checking whether sampled values match expected patterns. When degradation is detected (e.g., increased bit error rate or mismatch with expected synchronization patterns), the system provides feedback to adjust the sampling phase selection. This feedback mechanism enables adaptive response to signal deterioration while maintaining straightforward initial operation based on the synchronization sequence.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The sampling phase selection transitions from a static reference determined during synchronization to a dynamic selection that can change during frame transmission. The system can switch between different sampling phases depending on the current signal conditions, making the sampling timing adaptive rather than fixed. This dynamic approach allows the system to respond to phase noise, jitter, and other time-varying impairments.

Inventive Principle:
Principle #15Dynamics

3Reliability

If redundant error correction codes are used at high protocol levels, then bit errors can be corrected, but transmission efficiency decreases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidtransmission efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions to prevent errors before they occur by optimally selecting sampling phases based on signal quality assessment. By proactively adjusting sampling timing to avoid regions affected by phase noise or jitter, the system reduces the occurrence of bit errors in the first place. This preventive approach decreases the need for subsequent error correction, thereby improving transmission efficiency while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9065629B2Method and apparatus for regulating the sampling phase
Publication Date: 2015.06.23 INFINEON TECHNOLOGIES AG
  • US9065629B2 patent drawing
  • US9065629B2 patent drawing
  • US9065629B2 patent drawing

AI summary

Embodiments of the invention relate to methods and circuits for controlling the sampling phase of a signal that is to be regenerated by sampling, particularly a serial communication signal, having method steps or means for oversampling the signal in order to ascertain samples of the signal during predetermined sampling phases, for determining differential errors between the samples during different instances of the predetermined sampling phases, for determining a differential error rate between the samples to at least one first and at least one second sampling phase on the basis of the ascertained differential errors, and for comparing at least two differential error rates based on at least two different sampling phase pairs in order to ascertain a decision concerning which of the predetermined sampling phases can be selected as a reference sampling phase for correctly regenerating the signal.