Adaptive Scan Chain Diagnostic Pattern Generation
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Solution Overview
Problem
Current scan chain diagnosis methods in semiconductor manufacturing are inefficient in identifying timing faults and stuck-at faults in scan cell networks, particularly in complex scan chain architectures, which can lead to increased manufacturing costs and reduced yield due to the labor-intensive physical failure analysis processes.
Innovation Solution
The method involves loading and unloading scan cell networks with various scan chain patterns, including adaptive chain pattern lengths and reversible scan chain patterns, to collect and analyze test data, thereby identifying timing faults and stuck-at faults within the scan cell networks, and determining the location and type of faults using rule-based analysis and specific scan chain patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional scan chain diagnosis methods are used, then manufacturing process can be maintained, but diagnostic resolution is low and physical failure analysis requires significant time and effort
Solution Approach 1:
The patent segments the scan chain into multiple segments and applies different pattern lengths to each segment. By dividing the scan chain into manageable portions and testing them with optimized patterns, the system achieves higher diagnostic resolution without requiring exhaustive physical failure analysis of the entire chain, thereby reducing time loss.
Solution Approach 2:
The patent dynamically adjusts the scan chain pattern length based on the segment being tested and the suspected fault location. Rather than using fixed-length patterns, the system adapts pattern lengths to optimize diagnostic capability for each specific scenario, improving measurement precision while minimizing the time required to identify faults.
2Reliability
If comprehensive scan chain testing is performed to identify all faults, then manufacturing yield improves, but test time and complexity increase significantly
Solution Approach 1:
The patent applies partial testing by selecting specific pattern lengths and applying them to specific segments of the scan chain based on suspected fault locations. Rather than exhaustively testing every possible fault scenario, the system performs targeted testing that achieves sufficient diagnostic accuracy to improve manufacturing yield without the prohibitive time cost of complete testing.
Solution Approach 2:
The patent changes the parameter of pattern length to optimize testing efficiency. By varying the pattern length parameter based on the segment under test and the type of fault suspected, the system achieves effective fault identification that improves reliability while maintaining high productivity through reduced test time.
3Measurement precision
If fixed-length scan chain patterns are used, then testing is simpler, but timing faults and stuck-at faults cannot be accurately identified
Solution Approach 1:
The patent transitions from static fixed-length patterns to dynamic adaptive pattern lengths. The system automatically adjusts the pattern length based on the segment being tested and the characteristics of the suspected fault, enabling accurate identification of both timing faults and stuck-at faults while managing complexity through automated adaptation rather than manual configuration.
Solution Approach 2:
The testing system performs self-service by automatically selecting appropriate pattern lengths without requiring external intervention or complex manual setup. The system evaluates test results and autonomously adjusts pattern parameters to achieve accurate fault identification, reducing the burden on operators while maintaining high measurement precision.
Data Source
AI summary
A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.


